Transparent OLED Substrate Gate Line Arrangement
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Solution Overview
Problem
Existing transparent OLED display panels have a low resolution and a low proportion of transparent regions due to the large area occupied by gate lines, which limits the number of subpixels and the transparency of the display.
Innovation Solution
The display substrate design includes a base substrate with alternating transparent and display regions, where four subpixels are connected to the same gate line, reducing the number and area of gate lines, and arranging them between subpixel rows to facilitate wiring and ensure signal uniformity, while power supply and data lines are optimized to reduce their area and improve subpixel density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate lines are arranged in conventional configurations, then wiring is simplified, but the area occupied by gate lines increases, reducing transparent region proportion and display resolution
Solution Approach 1:
The patent applies dimensionality change by transitioning from conventional row-by-row gate line scanning to a hierarchical structure where gate lines extend in both row and column directions, creating a two-dimensional gate line network. This allows subpixels to be addressed through combinations of row and column gate lines, reducing the total number of gate lines needed while maintaining wiring simplicity.
Solution Approach 2:
The patent segments the gate line function by dividing the gate line network into row-direction and column-direction components. Instead of using single continuous gate lines, the system uses segmented gate lines that can be independently controlled, allowing for more efficient space utilization and reduced overall gate line area.
2Manufacturing precision
If more subpixels are arranged to increase resolution, then display quality improves, but the area occupied by gate lines and wiring increases, reducing transparent region proportion
Solution Approach 1:
The patent uses two-dimensional addressing where subpixels are located at intersections of row and column gate lines. This allows the number of subpixels to be significantly increased without a proportional increase in gate line area, as the gate lines serve multiple subpixels in both horizontal and vertical directions simultaneously.
Solution Approach 2:
Each gate line serves multiple functions by connecting to multiple subpixels across the display. Row gate lines and column gate lines work together to address any subpixel in the array, making the gate line network highly efficient and reducing the total wiring area required for high-resolution displays.
3Area of stationary object
If gate line area is reduced to increase transparent region proportion, then transparency improves, but wiring complexity and signal distribution difficulty increase
Solution Approach 1:
The gate line network is segmented into row and column components, each independently controllable. This segmentation simplifies signal distribution by allowing sequential scanning through rows and columns, reducing the complexity of simultaneously controlling all gate lines.
Solution Approach 2:
The patent implements periodic scanning of the gate line network, systematically activating row gate lines followed by column gate lines in a repeating cycle. This periodic action simplifies the control logic and signal distribution timing, making it easier to manage despite the reduced gate line area.
Data Source
AI summary
A display substrate and a display device are provided. The display substrate includes a base substrate, a plurality of pixels, a plurality of gate lines and a plurality of data lines, wherein the base substrate has a plurality of transparent regions and a plurality of display regions; the pixels are on the base substrate and within the display regions; each pixel includes a plurality of sub pixels; the sub pixels of each pixel are divided into two rows of sub pixels; the gate lines and the data lines are on the base substrate; the sub pixels of a first pixel are connected with the same gate line; the gate line connected with the sub pixels of the first pixel is between the two rows of sub pixels of the first pixel; and the first pixel is any one of the plurality of pixels.