Semiconductor Patterning With Transparent Sacrificial Overlay Marks

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Solution Overview

Problem

In semiconductor manufacturing, thicker hard masks used in high aspect ratio via patterning compromise overlay measurement quality due to increased opacity, leading to defocus and patterning failures caused by uneven topography differences between overlay mark and circuit areas.

Innovation Solution

A method involving a tri-layer resist structure and a sacrificial layer with varying coefficients of extinction is employed to improve overlay quality, where the sacrificial layer is transparent and has a lower coefficient than the insulating layer, allowing for accurate patterning and reduced topography differences, enabling improved focus and pattern resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If thicker hard masks are used in high aspect ratio via patterning, then via patterning capability is improved, but overlay measurement quality deteriorates due to increased opacity

Engineering Contradiction:
Improvehard mask thicknessVSAvoidoverlay measurement quality
Core Design Contradiction:
Length of moving objectVSMeasurement precision

Solution Approach 1:

The patent segments the overlay mark structure into multiple layers: a transparent sacrificial layer (first layer) and an opaque hard mask layer (second layer). This segmentation allows the hard mask to provide necessary thickness for via patterning while the transparent sacrificial layer beneath it allows optical measurement tools to see through to the overlay marks, resolving the contradiction between thickness and measurement quality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The transparent sacrificial layer acts as an intermediary between the opaque hard mask and the overlay marks. It mediates by allowing optical signals to pass through to the overlay marks while the hard mask provides the necessary physical thickness for high aspect ratio via patterning, thus enabling both thick hard mask usage and accurate overlay measurement

Inventive Principle:
Principle #24Intermediary (Mediator)

2Length of moving object

If thicker hard masks are used, then via patterning capability is improved, but topography uniformity deteriorates causing defocus and patterning failures

Engineering Contradiction:
Improvehard mask thicknessVSAvoidtopography uniformity
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the sacrificial layer transparent in specific areas where overlay marks are located, while the hard mask maintains its opaque property throughout. This localized transparency allows optical access to overlay marks in specific regions without compromising the overall thickness and structural integrity of the hard mask layer needed for via patterning

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The transparent sacrificial layer is formed and positioned beforehand to compensate for the topography issues that would arise from thick hard masks. This preliminary action creates a foundation that enables subsequent hard mask deposition at the required thickness while maintaining acceptable topography uniformity for patterning

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances overlay quality and pattern feature resolution, reducing line width roughness and increasing device yield by maintaining a consistent photoresist layer surface across the semiconductor device structure, facilitating accurate optical measurement without opaque hard masks.

Implementation Method 1

A method involving a tri-layer resist structure and a sacrificial layer with varying coefficients of extinction is employed to improve overlay quality, where the sacrificial layer is transparent and has a lower coefficient than the insulating layer

Methodology Applied
Scientific EffectCoefficient of extinction: Absorption (EM radiation)

Implementation Method 2

one or more planarization operations, such as a chemical mechanical polishing (CMP) process, are used to flatten a topography of a dielectric or conductive layer

Methodology Applied
Scientific EffectChemical mechanical polishing: Abrasion

Data Source

PatentUS11996297B2Method of manufacturing a semiconductor device
Publication Date: 2024.05.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11996297B2 patent drawing
  • US11996297B2 patent drawing
  • US11996297B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.