Transparent Display Panel Gate-Line Layout for Low Crosstalk
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Solution Overview
Problem
Current transparent display technologies face challenges in maintaining transparency while minimizing transmission impedance and avoiding signal crosstalk due to the arrangement of gate lines and data lines in the display panel.
Innovation Solution
The display panel design includes a base substrate with pixels having a light-transmitting area and a display area, where sub-pixel drive circuits are arranged with switching and detection transistors, and gate lines are positioned on both sides of the light-transmitting area to minimize impedance and prevent signal crosstalk by using integral structures for gate electrodes and connection lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate lines and data lines are arranged in conventional transparent display panels, then the display function is achieved, but transmission impedance increases and signal crosstalk occurs
Solution Approach 1:
The gate lines are extended into the light-transmitting area along the first direction (horizontal dimension) rather than being confined to the display area, changing the spatial arrangement from conventional vertical routing to a multi-dimensional layout that reduces impedance and crosstalk while maintaining transparency
2Object-affected harmful factors
If the gate lines are extended into the light-transmitting area, then transmission impedance is reduced and signal crosstalk is avoided, but the transparency may be affected
Solution Approach 1:
The gate lines are positioned specifically at the edges of the light-transmitting area and extend horizontally along the first direction, concentrating the conductive structures in locations that minimize impact on light transmission while effectively reducing impedance and crosstalk in the display area
Data Source
AI summary
The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; a pixel arranged on the base substrate, wherein the pixel includes a plurality of sub-pixel drive circuits sequentially arranged in the first direction in the display area, each of the sub-pixel drive circuits includes a switching transistor, a detection transistor and a storage capacitor, the switching transistor and the detection transistor are respectively located on both sides of the storage capacitor in a second direction; a first gate line configured to provide a first scanning signal to the plurality of sub-pixel drive circuits; and a second gate line configured to provide a second scanning signal to the plurality of sub-pixel drive circuits.