Transparent Root Complex for PCIe Device Sharing
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Solution Overview
Problem
In large computer networks, such as data centers, host computers face challenges in efficiently interacting with shared peripheral devices like network interface controllers (NICs), graphics processing units (GPUs), or storage devices, as existing solutions require software-based emulation and are not transparent to the host computer, complicating the management and access of these devices.
Innovation Solution
The implementation of a computing apparatus with a central processing unit (CPU) and a root complex connected to a peripheral component bus, utilizing switching logic that acts as a virtual switch to present peripheral devices in the address space of another bus, enabling transparent interaction and translation of bus transactions without the need for software-based emulation, allowing for hot-plugging of devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based emulation is used to allow host computers to access shared peripheral devices, then device sharing capability is improved, but system complexity and management overhead increase
Solution Approach 1:
The patent introduces a transparent root complex as an intermediary device that sits between the host computer's PCIe bus and the shared peripheral devices. This root complex performs address space translation and device presentation functions, allowing multiple hosts to access shared devices without requiring software-based emulation on each host. The intermediary handles the complexity of device sharing transparently, reducing system complexity while maintaining adaptability.
Solution Approach 2:
The patent segments the device access functionality by separating the transparent root complex from the host computers and shared peripheral devices. The root complex is divided into switching logic and address space translation components, allowing independent optimization and management of each function. This segmentation reduces the complexity burden on individual hosts while enabling flexible device sharing.
2Adaptability or versatility
If software-based emulation is implemented for peripheral device access, then device compatibility is improved, but access speed and efficiency deteriorate
Solution Approach 1:
The patent replaces software-based emulation with a hardware-based transparent root complex that performs address space translation and device presentation in hardware. This substitution eliminates the overhead of software emulation layers, providing direct hardware-level access to shared peripheral devices while maintaining compatibility through the translation capabilities of the root complex.
3Speed
If peripheral devices are physically connected to host computers, then access speed is improved, but device sharing and resource utilization deteriorate
Solution Approach 1:
The transparent root complex provides universal access to shared peripheral devices for multiple host computers through a common PCIe interconnect fabric. The switching logic within the root complex can dynamically route transactions from any host to any connected peripheral device, enabling one peripheral device to serve multiple hosts simultaneously with near-physical connection speeds.
4Ease of operation
If address space translation is implemented transparently, then ease of operation is improved, but processing overhead increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the address space translation mappings in the transparent root complex during system initialization or device enumeration. The switching logic and address translation tables are prepared in advance, allowing subsequent device access transactions to be translated with minimal processing delay rather than requiring complex runtime translation decisions.
Data Source
AI summary
Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.


