Self-Aligned Gate Transistor on Transparent Substrate
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Solution Overview
Problem
Current methods fail to fabricate self-aligned gate structures for carbon-based transistor devices, leading to parasitic capacitance issues that hinder circuit speed and frequency performance.
Innovation Solution
A method involving a transparent substrate, where a channel material is formed, source and drain electrodes are created, and a dielectric layer is deposited, followed by UV light exposure through the substrate to develop a photoresist, allowing for self-aligned gate metal deposition over the channel material, minimizing overlap with source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography methods are used for carbon-based transistors, then the fabrication process is simple, but the gate cannot be self-aligned to source and drain regions resulting in high parasitic capacitance
Solution Approach 1:
The patent performs photolithography exposure from the backside of the substrate through the transparent support, rather than from the front side. This dimensional change allows UV light to pass through the substrate and selectively expose photoresist in regions not blocked by source and drain electrodes, enabling self-aligned gate formation without modifying the front-side fabrication complexity
Solution Approach 2:
The transparent substrate acts as an intermediary medium that allows UV light to pass through during photolithography exposure. This mediator enables the photoresist on the front side to be exposed through the substrate from the back side, achieving self-aligned gate patterning while maintaining process simplicity
2Object-generated harmful factors
If gate overlap with source and drain regions is minimized, then parasitic capacitance is reduced, but achieving self-alignment requires complex fabrication techniques
Solution Approach 1:
Instead of attempting to deposit gate material only in the precise gap between source and drain electrodes (front-side alignment), the patent inverts the approach by exposing photoresist from the backside through the transparent substrate. Regions blocked by source and drain electrodes remain unexposed and protected, automatically creating the self-aligned gate pattern with minimal overlap
Solution Approach 2:
The source and drain electrodes serve a dual function: they act as both the functional transistor components and as the alignment mask for photolithography. The electrodes automatically define the gate region by blocking UV light, eliminating the need for separate alignment procedures and simplifying manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of transistor devices with reduced parasitic capacitance, enhancing circuit speed and frequency performance by achieving a self-aligned gate structure on carbon-based materials.
Implementation Method 1
The photoresist is developed using UV light exposure through the transparent substrate, wherein exposure of portions of the photoresist is blocked by the source and drain electrodes
Data Source
AI summary
Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.