Transponder Clock Gating for Stable RFID Frame Processing
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Solution Overview
Problem
RFID transponders face issues with command reception and response transmission due to voltage drops during digital processing, leading to errors in communication with readers, especially at lower field strengths and higher baud rates, and noise interference during response detection.
Innovation Solution
A transponder with digital logic, a status detection unit, and a clock gating unit that applies clock gating based on the status of data frame reception or transmission to control power consumption and reduce voltage variations, thereby minimizing errors and noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital logic continuously processes data frames in RFID transponders, then processing speed and communication throughput are improved, but voltage drops occur during processing leading to communication errors and reduced reliability
Solution Approach 1:
The patent implements periodic clock gating to the digital logic based on status detection. The clock signal is periodically enabled or disabled depending on whether data frame reception or transmission is actively occurring. This periodic action maintains processing capability when needed while preventing unnecessary voltage drops during idle periods, thus resolving the contradiction between processing speed and communication reliability
2Use of energy by moving object
If clock gating is applied to digital logic during idle periods, then power consumption is reduced, but processing delays may occur when data frame reception or transmission is needed
Solution Approach 1:
The patent employs a status detection unit that provides feedback about the current operational state (data frame reception or transmission status) to the clock gating control logic. This feedback mechanism ensures that clock gating is applied only when appropriate (during idle periods) and immediately removed when processing is needed, thus reducing power consumption without introducing unacceptable processing delays
3Speed
If digital logic operates at higher baud rates to improve communication speed, then data transmission efficiency is improved, but voltage drops and noise interference increase leading to detection errors
Solution Approach 1:
The patent extracts or removes the clock signal from the digital logic during periods when data frame reception or transmission is not actively occurring. By taking out the clock signal (clock gating), the digital logic enters a low-power state that prevents voltage drops and reduces noise interference, thereby eliminating the harmful effects that would otherwise limit the usable baud rate and detection accuracy
Data Source
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Figure 1A~1B
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AI summary
In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: digital logic for processing one or more portions of a data frame; a status detection unit configured to detect a status of a data frame reception or data frame transmission; a clock gating unit configured to apply clock gating to said digital logic in dependence on the status of said data frame reception or data frame transmission. In accordance with further aspects of the present disclosure, a corresponding method of operating a transponder is conceived, and a corresponding computer program is provided.