Transport Block Mapping Across Slot Boundaries in 5G PDSCH
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Solution Overview
Problem
Current wireless communication systems, particularly in 5G networks, face challenges in efficiently mapping transport blocks across allocated slots in physical shared channels, especially when resources are non-consecutive or when code blocks cross slot boundaries, leading to inefficiencies in data transmission.
Innovation Solution
The implementation of a transmit block processing chain that includes a code block determination circuit and a rate matching circuit, along with an interleaver, to determine the size of code blocks and rate-match bits across slot boundaries, ensuring efficient mapping and interleaving of data across allocated slots, even in cases where resources are non-consecutive.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If code blocks are mapped across slot boundaries in physical shared channels, then resource utilization is improved and data transmission efficiency is enhanced, but mapping complexity increases and slot boundary alignment becomes difficult
Solution Approach 1:
The code block is segmented into multiple code block groups (CBGs), where each CBG can be independently mapped to specific slots. This segmentation allows flexible distribution across slot boundaries while simplifying the mapping process by treating each CBG as a manageable unit with specific mapping rules based on slot aggregation type and redundancy version patterns.
Solution Approach 2:
The mapping approach dynamically adapts based on the slot aggregation type (Type A or Type B) and the specific slot configuration. The system selects different mapping strategies depending on whether resources are consecutive or non-consecutive, allowing optimal resource utilization while managing complexity through context-aware decision-making.
2Adaptability or versatility
If resources are allocated non-consecutively across slots, then resource flexibility is improved, but mapping continuity becomes challenging and implementation complexity increases
Solution Approach 1:
The system performs preliminary determination of the slot aggregation type and establishes the mapping strategy before actual code block mapping. This preliminary action includes identifying whether slots are consecutive or non-consecutive and selecting the appropriate mapping approach, which simplifies subsequent implementation by pre-resolving complexity issues.
Solution Approach 2:
The mapping approach changes parameters such as redundancy version assignment and code block group distribution based on the detected slot aggregation type. When slots are non-consecutive, the system adjusts the mapping parameters to ensure proper alignment and resource utilization, transforming the mapping behavior to match the resource allocation pattern.
3Productivity
If code blocks cross slot boundaries, then resource utilization efficiency is improved, but error resilience to quality degradations decreases
Solution Approach 1:
By segmenting the code block into multiple code block groups and mapping them to different slots with different redundancy versions, the system ensures that not all data is vulnerable to the same slot quality degradation. This segmentation provides diversity in error exposure and enables selective recovery of intact CBGs.
Solution Approach 2:
The system is designed to discard corrupted code block groups from degraded slots and recover data using intact CBGs from other slots. The mapping strategy ensures that sufficient redundant information is distributed across multiple slots, allowing the receiver to discard failed transmissions and recover the original data from successful receptions.
Data Source
AI summary
A system and a method are disclosed for processing data to be mapped into a transport block transmitted over a wireless physical shared channel. In one embodiment, a code block determination circuit determines a size of a code block of data that maps across at least one slot boundary of a slot of the wireless physical shared channel. A rate matching circuit rate matches bits of a code block to a number of bits available in the transport block that spans one or more slots of the wireless physical shared channel. An interleaver interleaves an output of the rate matching circuit so that a code block that crosses a slot boundary between a first slot and a second slot is interleaved between the first slot and the second slot.