Multi-Programme Transport Stream Controller Jitter Elimination

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Solution Overview

Problem

Current systems for processing multiple digital television streams, such as CIMaX®+, are limited in handling more than two concurrent streams and eight positive PID filters, leading to latency issues and jitter, which cause improper decoding and playback problems like freezing or skipping.

Innovation Solution

A multi-programme transport stream interface controller using a side-car Field-Programmable Gate Array (FPGA) is introduced to manage up to three transport streams, filter sixteen PIDs, and ensure constant packet delay, thereby eliminating jitter by inserting timing information and synchronizing packets accurately.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a system processes multiple concurrent transport streams using traditional methods, then the number of streams that can be handled is limited to two, but increasing the number of streams beyond two is desired

Engineering Contradiction:
Improvenumber of concurrent transport streams processedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the processing of multiple transport streams by assigning each stream a unique sync byte value (0x47 through 0x4E). This segmentation allows the conditional access module to independently identify and process up to eight different transport streams simultaneously, resolving the limitation of handling only two streams while maintaining manageable system complexity through structured organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interface controller is designed with universal functionality to handle multiple transport streams through a single unified interface. The system uses a generic marking process that can accommodate any number of streams within the supported range by dynamically assigning sync byte values, making the system adaptable to different numbers of concurrent streams without requiring separate processing paths

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If traditional PID filtering is used, then only up to eight positive PID filters are available, but sixteen PID filters are desired

Engineering Contradiction:
Improvenumber of PID filtersVSAvoidfiltering mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system extends the PID filtering capability by introducing an additional dimension of identification through sync byte values. Instead of relying solely on PID filtering, the system combines sync byte identification (providing 8 possible values) with PID filtering, effectively creating a two-dimensional filtering space that enables up to sixteen positive PID filters while maintaining manageable device complexity through the use of existing interface infrastructure

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If transport streams are processed without timing synchronization, then processing speed is maintained, but latency problems lead to jitter and improper decoding

Engineering Contradiction:
Improvedecoding accuracyVSAvoidpacket delay variation
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies preliminary timing synchronization by inserting timing information and adjusting packet timestamps before the transport streams are merged and processed by the conditional access module. This preliminary action ensures that packets are properly time-stamped and synchronized in advance, preventing jitter and decoding issues downstream while maintaining processing speed and reliability

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2852169B1A multi-programme transport stream common interface controller
Publication Date: 2017.11.08 SMARDTV SA
  • EP2852169B1 patent drawingFigure 1~2
  • EP2852169B1 patent drawingFigure 3
  • EP2852169B1 patent drawingFigure 4

AI summary

The present invention relates to simultaneous multi-stream processing of conditional access digital media content. The invention allows for the elimination of latency errors produced when merging a plurality of transport streams and uses a module comprising a timing mark inserter and a packet scheduler. The timing mark inserter inserts information useful for the packet scheduler to schedule the transport packet at the right time. One characteristic engendered by the packet scheduler is that the resulting partial transport stream has exactly the same clock as the corresponding multi-programme transport stream MPTS received from the corresponding tuner. The packet scheduler re-uses the information inserted by the timing mark inserter so that the time distance between 2 transport packets carrying programme clock reference (PCR) information is maintained, i.e. the number of transport packets between the 2 packets carrying PCR information stays the same.