Transpose Memory Unit for Multi-Bit CNN Computing-In-Memory

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Solution Overview

Problem

Current memory solutions for multi-bit convolutional neural network (CNN) based computing-in-memory (CIM) applications face challenges in reducing latency and power consumption while maintaining accuracy, particularly due to frequent weight updates and potential write disturb issues.

Innovation Solution

A transpose memory unit and array structure controlled by first and second word lines, incorporating memory cells and transpose cells that allow for simultaneous operation of multi-bit input values and weights without write disturb, utilizing local bit lines and multiple input/output word lines to generate multiply-accumulate output values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of operations is increased to enhance performance, then the processing capability is improved, but the latency and power consumption increase due to frequent weight updates

Engineering Contradiction:
Improveoperation numberVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The memory array is segmented into multiple banks (first bank, second bank, third bank, fourth bank) that can operate independently and simultaneously. This segmentation allows parallel processing of multiple operations without requiring sequential weight updates, thereby reducing latency while maintaining high operation numbers for enhanced productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Weights are pre-loaded into the memory banks before computation begins. The first weight is loaded into the first bank and the second weight is loaded into the second bank in advance, allowing the computing unit to perform multiple operations using these pre-loaded weights without requiring frequent updates during computation, thus reducing latency.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the number of operations is increased to enhance performance, then the processing capability is improved, but the power consumption increases due to frequent weight updates

Engineering Contradiction:
Improveoperation numberVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The memory array is segmented into multiple banks that can operate independently and simultaneously. This segmentation allows parallel processing of multiple operations without requiring sequential weight updates, thereby reducing power consumption while maintaining high operation numbers for enhanced productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Weights are pre-loaded into the memory banks before computation begins. The first weight is loaded into the first bank and the second weight is loaded into the second bank in advance, allowing the computing unit to perform multiple operations using these pre-loaded weights without requiring frequent updates during computation, thus reducing power consumption.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If weights are frequently updated to maintain accuracy, then the computation accuracy is improved, but the write disturb issue occurs

Engineering Contradiction:
ImproveaccuracyVSAvoidwrite disturb
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The memory array is segmented into multiple banks that can operate independently. This segmentation allows the system to maintain accuracy by having dedicated weight storage in each bank without requiring frequent writes to the same location, thereby preventing write disturb issues while maintaining computation accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Weights are pre-loaded into the memory banks before computation begins and remain stable during the computation process. This preliminary loading eliminates the need for frequent weight updates during computation, preventing write disturb issues while maintaining accuracy through the use of these stable pre-loaded weights.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11392820B2Transpose memory unit for multi-bit convolutional neural network based computing-in-memory applications, transpose memory array structure for multi-bit convolutional neural network based computing-in-memory applications and computing method thereof
Publication Date: 2022.07.19 NATIONAL TSING HUA UNIVERSITY
  • US11392820B2 patent drawing
  • US11392820B2 patent drawing
  • US11392820B2 patent drawing

AI summary

A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.