Transpose SRAM for AI Matrix Multiplication Power Reduction
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Solution Overview
Problem
In AI applications, matrix multiplication operations in semiconductor memory devices lead to increased power consumption and processing time due to frequent read operations from SRAM arrays, and writing high-potential-level data into flip-flop circuits results in higher current consumption.
Innovation Solution
A semiconductor memory device with a transpose SRAM configuration that allows data writing and reading in both row and column directions, utilizing cross-connected inverters and controlled wiring states to manage potential levels and reduce power consumption during writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an SRAM is used to store data for AI matrix multiplication operations, then data storage capability is provided, but power consumption increases due to frequent read operations
Solution Approach 1:
The SRAM is divided into multiple banks, allowing data to be stored in distributed segments. During matrix multiplication operations, different banks can be accessed simultaneously or selectively, reducing the frequency of read operations from a single bank and thereby lowering power consumption while maintaining overall data storage capability.
2Loss of time
If an SRAM capable of reading data from both row and column directions is used, then processing time is reduced, but current consumption increases during writing operations
Solution Approach 1:
The SRAM structure incorporates dynamic control mechanisms that adapt the writing operation based on the data state. When writing high-potential-level data, the assist operation is selectively applied only when necessary, rather than continuously. This dynamic adjustment reduces current consumption during writing while preserving the bidirectional reading capability that speeds up processing.
3Reliability
If an assist operation is applied to write high-potential-level data into a flip-flop circuit, then data writing reliability is improved, but current consumption increases
Solution Approach 1:
The assist operation modifies the potential level parameter dynamically during the writing process. By adjusting the gate potential of the access transistor only when writing high-potential-level data, the system improves writing reliability for critical cases while avoiding unnecessary current consumption during normal writing operations. This parameter-based selective assistance optimizes the trade-off between reliability and energy usage.
Data Source
AI summary
A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.