Transposed Select Gates for Memory Devices
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Solution Overview
Problem
In semiconductor memory devices, adjacent select gates experience significant capacitive coupling, leading to noise leakage and reduced accuracy in memory operations due to their close proximity, which increases power consumption and heating as memory cell density increases.
Innovation Solution
The select gates are transposed by separating them into segments and rearranging their interconnections, such that only portions of each select gate are adjacent to others, reducing capacitive coupling by configuring them to be adjacent for only a portion of their run, thereby minimizing leakage current and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If select gates are placed in close proximity to increase memory cell density, then memory device capacity is improved, but capacitive coupling between adjacent select gates increases causing noise leakage and reduced read accuracy
Solution Approach 1:
The bit line is divided into multiple segmented bit line portions, with each portion associated with a different select gate. This segmentation prevents capacitive coupling noise from affecting the entire bit line, as each segment is electrically isolated from others during different operational phases.
Solution Approach 2:
The patent implements dynamic control of select gates through phased enabling and disabling sequences. Select gates are enabled and disabled in different time phases, creating a dynamic operational regime where capacitive coupling effects are minimized through temporal separation of gate activities.
2Device complexity
If select gates are arranged in traditional adjacent configuration, then device simplicity is maintained, but noise leakage increases reducing read operation accuracy
Solution Approach 1:
The bit line is divided into multiple segmented bit line portions, with each portion associated with a different select gate. This segmentation prevents capacitive coupling noise from affecting the entire bit line, as each segment is electrically isolated from others during different operational phases.
Solution Approach 2:
The segmented bit line portions act as intermediaries between select gates, providing electrical isolation that prevents direct noise coupling while still allowing the select gates to control memory cells in proximity.
3Speed
If select gates operate simultaneously in close proximity, then operational speed is maintained, but power consumption and heating increase
Solution Approach 1:
The patent implements dynamic control of select gates through phased enabling and disabling sequences. Select gates are enabled and disabled in different time phases, creating a dynamic operational regime where capacitive coupling effects are minimized through temporal separation of gate activities.
Solution Approach 2:
The select gates operate in periodic phases rather than continuously simultaneously. Each select gate has specific time windows when it is active, creating a periodic action pattern that reduces continuous power consumption and heat generation while maintaining overall operational throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces capacitive coupling between select gates, leading to improved memory device performance with reduced noise, power consumption, and increased accuracy in read and program operations.
Implementation Method 1
Adjacent select gates can be capacitively coupled thereby permitting noise signals to leak from one select gate to another
Data Source
AI summary
Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates.