Transposed Via Arrangement for Probe Card Impedance Control

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Solution Overview

Problem

High-frequency signal transmission in probe card assemblies for semiconductor wafer testing faces impedance mismatch due to increased inductance between adjacent conductive structures, leading to signal reflections and loss.

Innovation Solution

A novel transposed via arrangement within the circuit board, where vias are offset to reduce inductance and impedance, and electromagnetic shielding is provided by surrounding ground vias to reduce crosstalk between signal vias, ensuring controlled impedance and improved signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional via arrangement is used, then manufacturing is simple, but inductance between adjacent vias increases causing impedance mismatch

Engineering Contradiction:
Improvesignal integrityVSAvoidvia arrangement complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by transposing the via arrangement from a symmetric grid pattern to an asymmetric configuration where vias are offset from their traditional positions. Specifically, signal vias are shifted relative to ground vias to maximize spacing between adjacent signal-carrying vias, thereby reducing inductance and impedance mismatch while maintaining manufacturing feasibility

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent addresses the via arrangement problem by considering three-dimensional spatial relationships rather than simple two-dimensional grid positioning. The transposed arrangement optimizes the spatial distribution of vias in multiple dimensions, creating optimized signal paths that reduce inductance while maintaining connection integrity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If vias are placed close together, then manufacturing precision is easier to achieve, but inductance increases causing signal loss

Engineering Contradiction:
Improvevia positioning accuracyVSAvoidsignal loss
Core Design Contradiction:
Manufacturing precisionVSLoss of energy

Solution Approach 1:

The asymmetric via arrangement allows signal vias to be positioned non-uniformly, with increased spacing between adjacent signal vias to reduce inductance and signal loss, while ground vias are strategically positioned to provide shielding without compromising manufacturing precision

Inventive Principle:
Principle #4Asymmetry

3Area of stationary object

If adjacent conductive structures are placed close together, then area is reduced, but crosstalk increases

Engineering Contradiction:
Improveprobe card areaVSAvoidcrosstalk
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent introduces ground vias as intermediary structures positioned between signal vias to provide electromagnetic shielding. These ground vias act as mediators that block electromagnetic fields from adjacent signal vias, reducing crosstalk while maintaining a compact probe card design

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The via arrangement applies different spacing strategies to different via types: signal vias are spaced farther apart to reduce crosstalk, while ground vias are positioned strategically to provide localized shielding where needed, creating a non-uniform but optimized spatial distribution

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces impedance mismatch and signal loss, enhancing high-frequency signal transmission and maintaining signal integrity by minimizing inductance and crosstalk, thereby improving the accuracy and efficiency of semiconductor wafer testing.

Implementation Method 1

High-frequency signal transmission in probe card assemblies for semiconductor wafer testing faces impedance mismatch due to increased inductance between adjacent conductive structures

Methodology Applied
Scientific EffectInductance: Inductor

Implementation Method 2

electromagnetic shielding is provided by surrounding ground vias to reduce crosstalk between signal vias

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS11333683B2Transposed via arrangement in probe card for automated test equipment
Publication Date: 2022.05.17 DIS TECH AMERICA LLC
  • US11333683B2 patent drawing
  • US11333683B2 patent drawing
  • US11333683B2 patent drawing

AI summary

A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a transposed via arrangement within a circuit board for a probe card, where adjacent vias are offset towards each other such that the inductance between the adjacent vias may be reduced to provide a desirable impedance during high frequency signal and/or power transmission.