Transverse Interface IC Inductor for Reduced Parasitics
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Solution Overview
Problem
Conventional inductors used in digital systems are large and bulky, leading to higher costs, assembly complications, and increased package size due to parasitics and size inefficiencies, particularly in integrated circuit (IC) fabrication where large inductors with higher quality factors and lower loss are desirable.
Innovation Solution
An integrated circuit (IC) inductor structure with transverse electrical interfaces is designed to minimize parasitics and size, featuring a first axis planar to a circuit layer surface that bisects the inductor into opposite sides, with input and output interfaces parallel to perpendicular axes, and three-dimensional loops formed over multiple circuit layers, optimizing space efficiency and circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inductor designs are used, then electrical performance (quality factor and loss) is improved, but device area and package size increase
Solution Approach 1:
The patent transitions from planar two-dimensional inductor layouts to three-dimensional multilevel structures with vertical stacking. Multiple circuit layers are utilized to create loops that extend in the vertical dimension, allowing inductors to achieve higher quality factors without proportionally increasing footprint area. The transverse interfaces connect layers vertically, enabling compact 3D configurations.
Solution Approach 2:
The patent implements nested inductor structures where smaller inductor loops are positioned within or adjacent to larger loops. Multiple turns and layers are arranged in nested configurations, maximizing the use of available space. This nesting allows multiple inductive elements to coexist in a compact footprint while maintaining desired electrical characteristics.
2Reliability
If large inductors are used, then quality factor increases and loss decreases, but manufacturing cost and assembly complexity increase
Solution Approach 1:
The patent combines multiple inductor functions and circuit elements into integrated multilevel structures. Inductors are fabricated using standard IC processing techniques that merge conductor traces, vias, and dielectric layers into unified structures. This integration reduces the number of discrete components and assembly steps while achieving low loss through optimized 3D current paths.
Solution Approach 2:
The patent optimizes electrical parameters by controlling conductor trace width, spacing, and layer stacking patterns. By adjusting geometric parameters during fabrication, the inductors achieve desired quality factors and loss characteristics without requiring oversized physical dimensions. Material selection and layer thickness are also optimized to minimize resistive losses.
3Ease of operation
If conventional inductor interfaces are used, then connectivity is achieved, but parasitic effects and space consumption increase
Solution Approach 1:
The patent introduces transverse interfaces that connect different circuit layers vertically through vias and through-silicon vias (TSVs). This vertical connectivity in the third dimension reduces the need for long horizontal interconnect traces, thereby minimizing parasitic inductance and resistance. The multilevel architecture allows signals to transition between layers with minimal parasitic accumulation.
Solution Approach 2:
The patent extracts and minimizes parasitic elements by optimizing interface designs. Connection points are strategically positioned to reduce parasitic inductance, and grounding schemes are implemented to eliminate parasitic coupling. Harmful parasitic effects are separated from the main inductive function through careful layout and shielding techniques.
Data Source
AI summary
An integrated circuit (IC) inductor structure is provided with transverse electrical interfaces. The inductor structure is formed on at least one IC circuit layer and has a first axis planar to a circuit layer surface, bisecting the inductor into opposite first and second sides. An input interface is formed on the circuit layer and connected to the inductor first side, parallel to a second axis, which is perpendicular to the first axis. An output interface is formed on the circuit layer and connected to the inductor second side, parallel to the second axis. In one aspect, the inductor has a center tap electrical interface parallel to the axis. In another aspect, the inductor includes a three-dimensional (3D) loop formed over a plurality of the circuit layers.