Trap Type Nonvolatile Memory Gate Insulating Layer Fabrication
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Solution Overview
Problem
The existing methods for fabricating trap type flash memory devices face challenges in forming three different thicknesses of gate insulating layers, leading to damage and thickness reduction of the upper silicon oxide layer during photolithography and subsequent processes, which affects the device's properties.
Innovation Solution
A method involving the formation of a cell gate insulating layer with a lower insulating layer, a charge storage layer, and an upper insulating layer sequentially stacked, followed by thermal annealing in a specific temperature range, and the use of a sacrificial layer pattern to prevent damage and ensure accurate etching, allowing for the formation of gate insulating layers with distinct thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the cell gate insulating layer is formed with thin upper silicon oxide layer to enable precise patterning, then the photolithography precision is improved, but the upper silicon oxide layer is damaged or thinned during photolithography and subsequent processes
Solution Approach 1:
The patent forms a thick sacrificial layer pattern before photolithography that protects the thin upper silicon oxide layer during subsequent processing. This preliminary protective structure prevents damage while allowing precise patterning to proceed, resolving the contradiction between achieving photolithography precision and maintaining layer integrity
Solution Approach 2:
The sacrificial layer pattern acts as an intermediary protective element between the photolithography process and the thin upper silicon oxide layer. This mediator absorbs the mechanical and chemical stresses of processing, preventing direct damage to the fragile oxide layer while enabling precise pattern formation
2Reliability
If three different thicknesses of gate insulating layer are formed to meet device requirements, then the device performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The gate insulating layer is segmented into three distinct thickness regions (thick in peripheral circuits, thin in cell arrays, and intermediate in mixed regions) to optimize device performance for different functional requirements. This segmentation allows each region to be tailored for its specific electrical characteristics while using a unified fabrication approach
Solution Approach 2:
The patent applies local quality by forming gate insulating layers with different thicknesses in different spatial regions of the semiconductor device. The cell array region receives a thin gate insulating layer for high-speed operation, while peripheral circuit regions receive a thick gate insulating layer for high voltage tolerance, optimizing each region's performance characteristics
3Reliability
If the upper silicon oxide layer is made thin to reduce equivalent oxide thickness, then the threshold voltage window is widened, but the breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by forming gate insulating layers with different thicknesses in different spatial regions of the semiconductor device. The cell array region receives a thin gate insulating layer for high-speed operation, while peripheral circuit regions receive a thick gate insulating layer for high voltage tolerance, optimizing each region's performance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents damage to the cell gate insulating layer, maintains its thickness, and improves the device's characteristics by widening the threshold voltage window and increasing the breakdown voltage, enhancing the overall performance of the nonvolatile memory device.
Implementation Method 1
thermal annealing in a specific temperature range
Data Source
AI summary
A method of fabricating a floating trap type nonvolatile memory device includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally annealing the cell gate insulating Layer at a temperature of approximately 810° C. to approximately 1370° C.; and forming a gate electrode on the thermally annealed cell gate insulating layer.