Trap Rich Layer for RF Substrate Parasitic Conduction
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Solution Overview
Problem
High resistivity substrates in semiconductor-on-insulator (SOI) technology are susceptible to parasitic surface conduction, leading to signal degradation and cross-talk in RF communication circuits, as they form inversion or accumulation regions under signal voltages, affecting capacitance and linearity.
Innovation Solution
A trap rich layer is formed at the top of the substrate to degrade carrier lifetimes and prevent parasitic surface conduction, which is introduced after active layer processing to preserve its integrity and avoid thermal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a trap rich layer is formed at the top of the substrate before active layer processing, then parasitic surface conduction is reduced, but the active layer integrity is degraded due to subsequent processing steps
Solution Approach 1:
The trap rich layer is formed at the top of the substrate before bonding the handle wafer to the semiconductor wafer, but after active layer processing is complete. This preliminary action allows the trap rich layer to be positioned correctly without exposing it to degradation from subsequent high-temperature processing steps that would occur if it were formed earlier
Solution Approach 2:
The handle wafer serves as an intermediary substrate that allows the trap rich layer to be formed and positioned correctly. The handle wafer is bonded to the semiconductor wafer after active layer processing, enabling the trap rich layer to reduce parasitic surface conduction without being exposed to degrading processing conditions
2Reliability
If the trap rich layer is introduced after active layer processing, then active layer integrity is preserved, but the effectiveness of reducing parasitic surface conduction may be compromised
Solution Approach 1:
The trap rich layer is formed in advance on the handle wafer before bonding, ensuring it is properly positioned and functional. By forming it preliminarily on the handle wafer rather than on the final substrate, it avoids degradation while still achieving the goal of reducing parasitic surface conduction at the correct location
Solution Approach 2:
The problem is solved by moving the trap rich layer formation to a different temporal and spatial dimension - forming it on the handle wafer before bonding rather than on the final substrate. This dimensional change in the process sequence allows the trap rich layer to be effective without exposure to degrading conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The trap rich layer effectively reduces parasitic surface conduction and substrate loss, enhancing RF performance by minimizing nonlinear capacitance and maintaining signal purity, while avoiding degradation from subsequent processing steps.
Implementation Method 1
A trap rich layer is formed at the top of the substrate to degrade carrier lifetimes and prevent parasitic surface conduction
Implementation Method 2
The trap rich layer effectively reduces parasitic surface conduction and substrate loss
Data Source
AI summary
A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.