Trap Rich Layer Placement in SOI RF Circuits
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Solution Overview
Problem
Semiconductor-on-insulator (SOI) technology faces challenges with parasitic surface conduction and cross-talk in RF communication circuits, particularly due to parasitic capacitance and signal-dependent nonlinearities, which degrade signal purity and performance.
Innovation Solution
A layer transferred structure with a trap rich layer in the handle wafer is introduced, positioned further away from the active layer than in traditional SOI structures, and formed after active layer processing to preserve its integrity and effectiveness, reducing parasitic surface conduction and nonlinear capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trap rich layer is formed in traditional SOI structures close to the active layer, then parasitic surface conduction is reduced, but the trap rich layer undergoes thermal degradation during high-temperature processing
Solution Approach 1:
The patent moves the trap rich layer from a position close to the active layer (traditional SOI) to a position further away in the handle wafer, effectively changing the spatial dimension of trap rich layer placement. This dimensional repositioning allows the trap rich layer to perform its function of reducing parasitic surface conduction while being shielded from thermal degradation during high-temperature processing of the active layer.
2Manufacturing precision
If the trap rich layer is positioned closer to the active layer, then signal purity is improved, but cross-talk between circuits increases
Solution Approach 1:
The patent applies local quality by creating a trap rich layer with specific electrical properties (high trap density) in a localized region of the handle wafer, positioned at an optimized distance from the active layer. This localized trap rich region provides signal purity benefits through parasitic conduction reduction while maintaining appropriate isolation to prevent cross-talk between adjacent circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances RF performance by minimizing parasitic surface conduction and substrate loss, maintaining signal purity and reducing cross-talk, while avoiding thermal degradation of the trap rich layer during high-temperature processing.
Implementation Method 1
A trap rich layer is formed in a handle wafer... reducing parasitic surface conduction and nonlinear capacitance
Data Source
AI summary
An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.