Trap-Rich Polysilicon Isolation for RF SOI Linearity
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Solution Overview
Problem
High-frequency radio frequency (RF) devices face challenges due to voltage imbalances and parasitic capacitance effects in semiconductor-on-insulator (SOI) FET switches, leading to non-linearity issues, which are difficult to address with existing manufacturing and assembly methods.
Innovation Solution
A semiconductor device is manufactured with a trap-rich polysilicon layer embedded within the substrate, forming isolation trenches and lateral cavities to minimize parasitic capacitance, providing both vertical and horizontal isolation and reducing non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor-on-insulator FET switches are used in RF devices, then integration and compactness are improved, but parasitic capacitance and voltage imbalances increase causing non-linearity
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitance by creating isolation trenches that physically separate the FET switch from the substrate. The trenches extend through the substrate and are filled with dielectric material, effectively extracting the parasitic capacitance path from the device structure.
Solution Approach 2:
The patent introduces an intermediary isolation structure between the FET switch and the substrate. This includes isolation trenches filled with dielectric material and trap-rich polysilicon layers that act as mediators to block parasitic capacitance while maintaining device functionality.
2Object-generated harmful factors
If isolation trenches are formed through the substrate, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the isolation process into distinct stages: forming isolation trenches through the substrate, filling them with dielectric material, and adding trap-rich polysilicon layers. This segmentation allows each step to be optimized independently and integrated into existing manufacturing workflows.
Solution Approach 2:
The patent performs preliminary actions by forming trap-rich polysilicon layers before final device assembly. These layers are prepared in advance within the isolation trenches, ensuring parasitic capacitance is minimized before the device is fully assembled and tested.
3Reliability
If trap-rich polysilicon layers are added, then linearity is improved by minimizing parasitic capacitance, but device structure becomes more complex
Solution Approach 1:
The patent applies local quality by placing trap-rich polysilicon layers specifically in the isolation trenches beneath and around the FET switch, rather than uniformly throughout the entire device. This localized application targets the specific areas where parasitic capacitance occurs, improving linearity without unnecessarily complicating the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes parasitic capacitance and non-linearity in RF devices, enhancing their linearity specifications and performance, particularly in high-frequency applications.
Implementation Method 1
A trap-rich layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or mitigate parasitic surface conduction effects
Implementation Method 2
forming an isolation trench through a first semiconductor layer of a semiconductor substrate and partially through an isolation layer that underlies the first semiconductor layer
Data Source
AI summary
A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.