Trap-Rich SOI Substrate for RF Cross-Talk Suppression
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Solution Overview
Problem
Silicon-on-insulator (SOI) substrates using high resistivity handle wafers suffer from parasitic surface conduction and device cross-talk due to accumulation layers, leading to non-linear distortion in RF signals.
Innovation Solution
Incorporation of a trap-rich layer with a high density of electrically-active carrier traps, such as arsenic diffused into the silicon substrate, to reduce carrier lifetime and mobility, thereby minimizing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high resistivity handle wafers are used in SOI substrates, then device-to-device isolation and passive component Q-factors are improved, but parasitic surface conduction and device cross-talk occur due to accumulation layers forming at the handle wafer surface
Solution Approach 1:
A trap-rich layer is introduced as an intermediary between the high resistivity handle wafer and the active silicon layer. This layer acts as a mediator that captures carriers before they can form accumulation layers at the handle wafer surface, thereby eliminating parasitic surface conduction while preserving the isolation benefits of the high resistivity substrate.
Solution Approach 2:
The invention converts the harmful effect of carrier accumulation into a beneficial trap-rich region. By intentionally creating a layer with high carrier trapping capability through doping or defect introduction, the potential harmful accumulation layer is transformed into a useful trap-rich layer that actively suppresses parasitic conduction paths.
2Reliability
If high resistivity handle wafers are used in SOI substrates, then passive component Q-factors are improved, but non-linear distortion is introduced into RF signals due to accumulation layers
Solution Approach 1:
The trap-rich layer serves as an intermediary that prevents the formation of accumulation layers responsible for non-linear distortion. By capturing carriers in the trap-rich layer, the interface between the handle wafer and active layer remains free of charge accumulation, thereby eliminating the source of non-linear distortion while preserving Q-factor performance.
3Reliability
If doping is reduced in handle wafers to achieve high resistivity, then device-to-device isolation is improved, but carrier accumulation occurs at the handle wafer surface forming accumulation or inversion layers
Solution Approach 1:
The trap-rich layer acts as an intermediary that stabilizes carrier distribution. It provides a controlled region for carrier trapping that prevents uncontrolled accumulation at the handle wafer surface, thereby stabilizing the electrical composition while maintaining the low-doping conditions necessary for good device isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The trap-rich layer significantly decreases parasitic surface conduction and device cross-talk, enhancing signal integrity and reducing non-linear distortion in RF signals.
Implementation Method 1
Incorporation of a trap-rich layer with a high density of electrically-active carrier traps, such as arsenic diffused into the silicon substrate, to reduce carrier lifetime and mobility
Implementation Method 2
arsenic diffused into the silicon substrate
Data Source
AI summary
A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.