Trapezoid Photosensitive Chip Layout for Faster Wafer Singulation
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Solution Overview
Problem
Conventional methods for singulating photosensitive chips using plasma etching are costly, time-consuming, and result in low yield rates, especially for wafers with thicknesses of 100 to 300 micrometers, limiting the production efficiency and increasing costs.
Innovation Solution
The use of an isosceles trapezoid-shaped photosensitive chip design allows for traditional straight cutting processes, replacing plasma etching, and the integration of a conductive circuit board with isosceles trapezoid-shaped photosensitive chips arranged to maximize light-receiving area and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma etching process is used for singulation, then photosensitive chips can be produced, but production cost increases, processing time extends, and yield rate decreases
Solution Approach 1:
The patent segments the singulation process into two stages: first cutting grooves at predetermined positions during wafer fabrication, then completing the separation after chip fabrication. This allows the use of simpler, faster cutting methods instead of requiring complete plasma etching through the entire wafer thickness, thereby improving productivity while maintaining precision.
Solution Approach 2:
The patent performs preliminary cutting actions by forming grooves at predetermined positions during the wafer fabrication stage, before the chips are fully fabricated. This preliminary action reduces the subsequent singulation workload and enables the use of more efficient cutting methods, resolving the contradiction between precision and productivity.
2Manufacturing precision
If plasma etching process is used for singulation, then photosensitive chips can be produced, but production cost increases
Solution Approach 1:
The patent segments the singulation process into two stages: first cutting grooves at predetermined positions during wafer fabrication, then completing the separation after chip fabrication. This allows the use of simpler, faster cutting methods instead of requiring complete plasma etching through the entire wafer thickness, thereby reducing production cost while maintaining precision.
Solution Approach 2:
The patent employs conventional cutting blades for the second-stage singulation instead of expensive plasma etching equipment, using cheaper tools to complete the separation process after the preliminary grooves have been formed, thus reducing overall manufacturing cost.
3Manufacturing precision
If plasma etching process is used for singulation, then photosensitive chips can be produced, but processing time extends
Solution Approach 1:
The patent segments the singulation process into two stages: first cutting grooves at predetermined positions during wafer fabrication, then completing the separation after chip fabrication. This allows the use of simpler, faster cutting methods instead of requiring complete plasma etching through the entire wafer thickness, thereby reducing processing time while maintaining precision.
Solution Approach 2:
The patent performs preliminary cutting actions by forming grooves at predetermined positions during the wafer fabrication stage, before the chips are fully fabricated. This preliminary action reduces the subsequent singulation workload and enables the use of more efficient cutting methods, resolving the contradiction between precision and processing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces production costs and time, improves yield rates, and enhances the light-receiving area by approximately 2%, leading to power savings and design flexibility for smart wearable devices.
Implementation Method 1
When light is incident on the photosensitive chip, it can generate corresponding changes in current or voltage
Data Source
AI summary
A photosensitive chip, a manufacturing method thereof, and a photosensitive module are provided. The photosensitive chip includes an isosceles trapezoid body, a positive electrode, and a negative electrode. The isosceles trapezoid body comprises an N-type semiconductor layer and a P-type semiconductor layer. The P-type semiconductor layer is disposed adjacent to the N-type semiconductor layer. The positive electrode is electrically connected to the P-type semiconductor layer, and the negative electrode is electrically connected to the N-type semiconductor layer.