Trapezoidal Charge Storage Structure for Flash Memory Cells
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Solution Overview
Problem
Flash memory devices, particularly NAND flash memory, face performance limitations due to interference between floating gates, slower programming and erasing speeds, and smaller program-erase windows, which are not adequately addressed by increasing unit cell dimensions.
Innovation Solution
The solution involves altering the shape and size of charge storage structures, such as floating gates, to non-rectangular shapes like trapezoidal configurations, with vertically oriented conductive channels and insulative layers, to improve cell performance by reducing capacitance and interference, and optimizing the geometry of dielectric layers to enhance programming and erasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If unit cell dimensions are increased to improve programming and erasing speeds, then speed improves, but device density and scalability deteriorate
Solution Approach 1:
The patent applies asymmetry by changing the charge storage structure from a conventional rectangular shape to a trapezoidal shape. The trapezoidal configuration has a wider base and narrower top, creating an asymmetric geometry that reduces the effective area occupied by each cell while maintaining sufficient charge storage capacity. This asymmetric design allows for tighter cell spacing and improved device density without compromising programming and erasing speeds.
Solution Approach 2:
The patent employs parameter changes by modifying the geometric parameters of the charge storage structure. Specifically, the trapezoidal shape alters the distribution of electric fields and charge storage density within the cell. By optimizing the angles and dimensions of the trapezoidal structure, the patent achieves improved programming and erasing speeds while reducing the overall unit cell area, thereby resolving the contradiction between speed and density.
2Ease of manufacture
If conventional rectangular charge storage structures are used, then manufacturing is simple, but interference between floating gates increases and performance deteriorates
Solution Approach 1:
The trapezoidal charge storage structure introduces asymmetry that naturally reduces the overlap and interference between adjacent floating gates. The angled sides of the trapezoid create greater spacing between neighboring cells compared to rectangular structures, thereby reducing parasitic capacitance and interference. This geometric modification maintains manufacturability through standard semiconductor fabrication processes while significantly improving cell performance.
Solution Approach 2:
While not fully spherical, the patent applies a form of curvature by using angled and rounded transitions in the trapezoidal structure rather than sharp rectangular corners. This curved geometry helps distribute electric fields more evenly and reduces field concentration at corners, thereby minimizing interference between adjacent cells and improving overall device performance.
3Device complexity
If rectangular charge storage structures are used, then device structure is simple, but program-erase window size is limited
Solution Approach 1:
The asymmetric trapezoidal geometry creates an optimized electric field distribution that enhances the program-erase window. The wider base provides greater charge storage capacity while the narrower top reduces interference with control gates. This asymmetric configuration enlarges the program-erase window, improving reliability and data retention without significantly increasing device complexity.
Solution Approach 2:
By changing the geometric parameters from a rectangular to a trapezoidal configuration, the patent optimizes the electric field strength and distribution during programming and erasing operations. The specific angles and dimensions of the trapezoid are designed to maximize the program-erase window, thereby improving reliability while maintaining reasonable structural complexity.
Data Source
AI summary
Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.