Traversal Stack Compression for Ray Tracing Memory Bandwidth

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional traversal stacks in ray tracing and other operations consume a large portion of available memory bandwidth due to memory traffic, as each node is stored individually, leading to inefficient memory usage and performance.

Innovation Solution

A method for performing traversal stack compression by creating stack entries that contain multiple intersected nodes and storing them in a compressed format, reducing memory usage and traffic by representing multiple nodes as a single entry, thereby increasing available processing memory bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional traversal stacks store each node individually, then node access is simple and direct, but memory bandwidth consumption increases significantly

Engineering Contradiction:
Improvenode access simplicityVSAvoidmemory bandwidth consumption
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The patent merges multiple individual node storage operations into a single batched traversal stack entry. Instead of pushing each intersected node separately onto the traversal stack, the system accumulates multiple node indices and pushes them as a single batched entry, reducing memory transaction overhead while maintaining traversal functionality

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the parameter of stack entry structure from individual node storage to batched node storage. Each traversal stack entry contains multiple node indices packed together, transforming the data structure from fine-grained individual nodes to coarse-grained batches, thereby reducing memory bandwidth consumption

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If individual nodes are stored in the traversal stack, then memory access patterns are simple, but memory traffic consumes a large portion of available bandwidth

Engineering Contradiction:
Improvememory access pattern simplicityVSAvoidprocessing efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent combines multiple node push operations into a single batched push operation. The traversal stack processes nodes in batches rather than individually, merging multiple memory write operations into one transaction, which simplifies the overall memory access pattern while increasing processing efficiency by reducing memory traffic overhead

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If multiple nodes are stored as a single stack entry, then memory consumption and traffic are reduced, but the structure of stack entries becomes more complex

Engineering Contradiction:
Improvememory consumptionVSAvoidstack entry structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the batched node data into fixed-size groups that fit within single memory transactions. By dividing the batched node indices into manageable segments that align with memory transaction boundaries, the system reduces memory traffic while keeping the stack entry structure relatively simple and predictable

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10984049B2Performing traversal stack compression
Publication Date: 2021.04.20 NVIDIA CORP
  • US10984049B2 patent drawing
  • US10984049B2 patent drawing
  • US10984049B2 patent drawing

AI summary

A method, computer readable medium, and system are disclosed for performing traversal stack compression. The method includes traversing a hierarchical data structure having more than two children per node, and during the traversing, creating at least one stack entry, utilizing a processor, where each stack entry contains a plurality of intersected nodes, and adding the at least one stack entry to a compressed traversal stack stored in a memory, utilizing the processor.