Treated Dielectric Films Under Source/Drain Recesses for Leakage Control
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, issues such as increased leakage between source/drain regions and the underlying substrate, and elevated parasitic capacitance between gate electrodes and source/drain regions become significant challenges.
Innovation Solution
The implementation of a treatment process for dielectric layers deposited in source/drain recesses, which enhances the quality and resistance of these layers to subsequent etching and cleaning processes, thereby reducing leakage and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric layers are deposited in source/drain recesses without treatment, then the fabrication process is simpler, but leakage current increases and etching resistance decreases
Solution Approach 1:
A treatment process is performed on the dielectric layer after deposition but before subsequent etching steps. This preliminary treatment enhances the etching resistance of the dielectric layer, preventing excessive etching and reducing leakage current between source/drain regions.
Solution Approach 2:
The treatment process modifies the physical or chemical parameters of the dielectric layer, such as its density, cross-linking, or surface properties, to improve its resistance to subsequent etching processes and reduce leakage current.
2Reliability
If dielectric layers are treated to improve etching resistance, then leakage current is reduced, but the fabrication process becomes more complex
Solution Approach 1:
The treatment process is integrated into the fabrication sequence as a preliminary step before etching, ensuring the dielectric layer is properly prepared to resist subsequent etching attacks and prevent leakage current issues.
Solution Approach 2:
The treatment process acts as an intermediary step between dielectric deposition and etching, modifying the dielectric layer properties to bridge the gap between these two processes and ensure proper etching resistance.
3Productivity
If minimum feature sizes are reduced to increase integration density, then more components fit in given area, but leakage and parasitic capacitance increase
Solution Approach 1:
The treatment process is applied specifically to dielectric layers in source/drain recesses, providing localized improvement in etching resistance and leakage current prevention where it is most needed, without affecting the entire device structure.
Solution Approach 2:
By modifying the dielectric layer parameters through treatment, the invention enables smaller feature sizes to be used while maintaining adequate etching resistance and minimizing leakage current, thus supporting higher integration density.
Data Source
AI summary
A method includes forming a gate stack over a semiconductor region, etching the semiconductor region to form a source/drain recess aside of the gate stack, depositing a first dielectric layer, wherein a portion of the first dielectric layer is in the source/drain recess, performing a treatment process on the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, and etching the second dielectric layer and the first dielectric layer. A first portion of the first dielectric layer and a second portion of the second dielectric layer remain at a bottom of the source/drain recess to form a dielectric region. A source/drain region is deposited in the source/drain recess and over the dielectric region.