Tree-Like Cache Hierarchy for Multi-Core Processor Scalability
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Solution Overview
Problem
Traditional cache systems in multi-processor architectures face inefficiencies due to data duplication and coherency management issues, particularly with ring bus structures that limit scalability and consume significant time and energy.
Innovation Solution
A tree-like memory hierarchy structure where each core has a coupled cache and local memory, connected via a tree-like communication structure to a higher level cache, allowing efficient data transfer and minimizing data duplication by identifying a 'preferred owner' for cache lines based on access frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a ring bus structure is used to connect caches in multi-core processors, then data can be transferred between caches, but scalability is limited and energy consumption increases
Solution Approach 1:
The patent segments the cache system into multiple independent cache modules (L1 caches associated with individual cores and L2 caches organized in a tree structure). Each cache operates semi-independently with its own management logic, allowing the system to scale by adding more cache modules without requiring a complete reconfiguration of the interconnection structure. This segmentation eliminates the need for a centralized ring bus while maintaining data transfer capabilities.
Solution Approach 2:
The patent transitions from a one-dimensional ring bus topology to a two-dimensional tree-like hierarchy structure. The tree structure organizes caches in multiple levels (L1, L2, L3) with parent-child relationships, enabling data transfer through multiple paths and reducing the communication distance between caches. This dimensional change improves scalability by allowing parallel data transfer operations and reducing the overhead on any single communication channel.
2Reliability
If data is transferred between caches to maintain coherency, then coherency is maintained, but time and energy are consumed
Solution Approach 1:
The patent implements preliminary actions by pre-establishing the tree-like hierarchy structure with defined parent-child relationships between caches before data transfer operations begin. Each cache is pre-configured with information about its siblings and parent, allowing for direct routing of coherency messages without dynamic path computation. This pre-organization reduces the time required for coherency maintenance operations.
Solution Approach 2:
The patent introduces L2 caches as intermediary nodes between L1 caches and L3 caches in the tree hierarchy. When data coherency needs to be maintained between caches, the intermediary L2 caches handle the transfer operations, reducing the time and energy required compared to direct transfers across the entire system. The intermediaries can also buffer and manage multiple coherency requests simultaneously.
3Speed
If data is duplicated in multiple caches, then data is readily accessible, but memory space and power are wasted
Solution Approach 1:
The patent applies local quality by allowing data duplication only in specific locations within the tree hierarchy based on access patterns and locality requirements. Frequently accessed data is replicated in L1 caches associated with cores that access it frequently, while less frequently accessed data resides in higher-level L2 or L3 caches. This selective duplication maintains fast access speed for critical data while minimizing overall memory space consumption compared to universal duplication.
Solution Approach 2:
The patent implements dynamic data placement and duplication strategies where the location and replication status of data in the cache hierarchy changes based on runtime access patterns. The system can dynamically promote data from lower-level caches to higher-level caches or replicate data to specific L1 caches based on observed access behavior. This dynamic approach optimizes the balance between data access speed and memory space utilization.
Data Source
AI summary
The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.