Tree Clock Distribution for DRAM Timing Alignment
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Solution Overview
Problem
In dual in-line memory modules (DIMMs), achieving accurate clocking of command and address signals across multiple DRAM devices is challenging due to varying distances and load capacitances, leading to clock skewing and potential memory reading/writing inaccuracies, as existing designs struggle to ensure complete clock training across all devices.
Innovation Solution
A tree structure for clock lines is implemented, allowing each clock signal to be individually trained and aligned with command and address signals at each DRAM device location, using a controller to distribute and adjust clock signals through a clock buffer, ensuring temporal alignment with the command and address signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock lines are routed similarly to command and address signals in a daisy-chained DIMM, then the load capacitance is distributed to accommodate high-speed signaling, but significantly different delays of clock signals occur at different DRAM devices due to varying distances and load capacitances
Solution Approach 1:
The clock distribution system is segmented into multiple independent clock lines, each dedicated to a specific DRAM device or group of devices. This segmentation allows each clock line to be individually optimized and trained, eliminating the cumulative delay issues of daisy-chained clock distribution while maintaining high-speed data transfer capability.
Solution Approach 2:
Clock training is performed in advance during the initialization phase to pre-adjust the timing of each clock signal. By performing preliminary clock training, the system establishes accurate timing relationships before actual data transfer operations begin, ensuring reliable clocking throughout subsequent high-speed operations.
2Productivity
If multiple DRAM devices are connected with significantly different distances and load capacitances to command and address lines, then daisy chaining allows high data rates, but timing alignment of clock signals with command and address signals becomes significantly different across devices
Solution Approach 1:
Each clock line is configured with local quality characteristics tailored to its specific DRAM device or group, including individual timing adjustments and training parameters. This local optimization ensures that each device receives a clock signal precisely aligned with its command and address signals, regardless of position in the memory module.
Solution Approach 2:
The system dynamically adjusts clock signal parameters such as phase, frequency, and timing offsets for each individual clock line based on measured characteristics of the connected DRAM devices. These parameter changes enable precise timing alignment across devices with varying distances and load capacitances.
Data Source
AI summary
A computing system including multiple integrated circuit memory devices is described. One or more command and address buses are connected to the memory devices to transmit command and address signals to each memory device. Multiple clock lines are connected to the multiple memory devices in a tree structure to transmit multiple clock signals to these memory devices. The tree structure allows each distributed clock signal to be individually trained such that the multiple clock signals provide each memory device with a clock signal that is temporally aligned with the command and address signals as received by that memory device.