Tree-coded Video Compression with Coupled Parallel Pipelines

The patent divides the processing of different coding unit sizes into separate parallel pipelines. Each pipeline is dedicated to a specific coding unit size (e.g., 64×64, 32×32, 16×16, 8×8), allowing simultaneous exploration of mode decisions for all sizes without requiring a single complex device to handle all sizes sequentially. This segmentation enables quality improvement through parallel processing while managing hardware complexity by creating specialized, simpler pipeline units.

The patent introduces a new dimension of processing by organizing pipelines in a hierarchical structure corresponding to the quad-tree partitioning levels. Instead of using multiple independent devices at the same level, the solution creates a multi-level pipeline architecture where pipelines at different hierarchy levels process coding units of different sizes simultaneously. This dimensional organization allows efficient resource utilization and reduces overall hardware area requirements.

The patent implements periodic action through its pipelined architecture where each pipeline processes coding units in regular, rhythmic intervals. The pipelines are designed to complete processing of one coding unit size and immediately transition to the next, creating a periodic flow of processed data. This periodic operation enables efficient time management and reduces synchronization overhead by establishing predictable processing cycles across all pipelines.

The patent ensures continuity of useful action by designing the pipelines to operate continuously without idle periods. Each pipeline maintains a steady stream of processing operations, and the hierarchical structure allows higher-level pipelines to continuously receive and process results from lower-level pipelines. This continuous operation maximizes throughput and minimizes processing time while maintaining quality exploration across all coding unit sizes.

The patent merges multiple processing functions into a unified hierarchical pipeline architecture. Instead of using separate hardware for each coding unit size, the solution combines all size-specific processing into an integrated system where pipelines at different hierarchy levels work together. This merging approach improves productivity through parallel processing while controlling hardware area by sharing common resources and structures across the unified architecture.

The patent implements universality by designing the hierarchical pipeline architecture to handle multiple coding unit sizes within a single system. Each pipeline is designed with multi-functional capabilities to process different types of data and perform various operations depending on the coding unit size being processed. This universal design improves processing efficiency without requiring separate specialized hardware for each function, thereby controlling overall hardware area.