Tree-Topology Memory Buffer Architecture for Latency Reduction
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Solution Overview
Problem
The existing memory access systems experience high access delays due to the need for series connection of Advanced Memory Buffer (AMB) chips, which increases the time required to access memory modules, especially those farther away, and necessitates conversion from series to parallel protocol, hindering memory access efficiency.
Innovation Solution
A memory access method involving a memory controller, first and second level buffer chips, where the memory controller sends a memory access instruction and address signals to the first level buffer chip, which processes and forwards them to the second level buffer chip, allowing for a tree-like topological cascading of memory access, eliminating the need for series to parallel protocol conversion and reducing access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Advanced Memory Buffer (AMB) chips are connected in a series manner to expand system memory capacity, then the access capacity of system memory is increased, but the access delay is increased due to protocol conversion and longer signal paths
Solution Approach 1:
The patent segments the buffer chip into multiple independent buffer units, each capable of handling memory access requests independently. This segmentation allows parallel processing of multiple requests, reducing the overall access delay while maintaining expanded memory capacity through the series connection of buffer chips.
Solution Approach 2:
The patent transitions from a single-series buffer chip architecture to a multi-dimensional architecture where multiple buffer units operate in parallel within each buffer chip. This dimensional change enables simultaneous signal reception and processing across different buffer units, eliminating the need for sequential protocol conversion and reducing access delay.
2Quantity of substance
If series connection is used between buffer chips, then memory capacity is expanded, but protocol conversion from series to parallel is required which increases access delay
Solution Approach 1:
The patent extracts the protocol conversion function from the buffer chip architecture by implementing independent buffer units that can directly handle parallel requests. This removes the need for complex series-to-parallel protocol conversion within the buffer chip, simplifying the device complexity while maintaining expanded memory capacity through series connection of the buffer chips themselves.
3Quantity of substance
If Advanced Memory Buffer chips are added to expand memory capacity, then access capacity is increased, but the distance for signal transmission increases causing higher delay for farther memory modules
Solution Approach 1:
The patent introduces multiple independent buffer units as intermediaries between the memory controller and memory modules. Each buffer unit can independently receive and process requests, acting as a local mediator that reduces the effective signal transmission distance. This allows the system to maintain expanded access capacity while reducing delay for farther memory modules through parallel intermediate processing points.
Data Source
AI summary
A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delay processing on a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem and reduces the memory access time.