Trellis-Assisted Bit-Flipping Decoder for Irregular LDPC Codes

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Bit flipping (BF) decoders struggle with low error correction capability and inefficiency in handling irregular low-density parity-check (LDPC) codes, leading to prolonged decoding times or failure in correcting small error sets, while min-sum (MS) decoders are slow and costly in terms of power and chip area.

Innovation Solution

A trellis-assisted BF decoder is used to enhance error correction by concurrently executing multiple trellis decoders to resolve unsatisfied check nodes, improving decoding efficiency without additional latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If bit flipping (BF) decoding is used for LDPC code decoding, then decoding speed is improved, but error correction capability deteriorates

Engineering Contradiction:
Improvedecoding speedVSAvoiderror correction capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The decoding process is segmented into two distinct parts: a BF decoder that handles the majority of decoding tasks at high speed, and a trellis decoder that specifically handles the remaining unsatisfied check nodes. This segmentation allows each decoder to operate in its optimal performance regime, with the BF decoder providing speed and the trellis decoder providing enhanced error correction capability for difficult cases.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The trellis decoder acts as an intermediary that receives unsatisfied check node information from the BF decoder and provides refined bit value determinations back to the BF decoder. This intermediary role allows the system to leverage both decoders' strengths without requiring the BF decoder to handle all error correction tasks alone.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If irregular LDPC codes are used to improve MS decoder performance, then error correction capability is improved, but BF decoder performance deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoidBF decoder performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system applies different decoding strategies to different parts of the code structure. The BF decoder handles variable nodes with sufficient information locally, while the trellis decoder provides enhanced processing for specific unsatisfied check nodes. This local quality approach allows irregular codes to maintain their error correction advantages while the BF decoder continues to operate efficiently on suitable portions of the decoding task.

Inventive Principle:
Principle #3Local quality

3Reliability

If more complex decoding algorithms are used to improve error correction capability, then reliability is improved, but computation cost increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Instead of applying the computationally intensive trellis decoding algorithm to all check nodes, the system applies it only to the subset of unsatisfied check nodes that remain after BF decoding. This partial action approach provides the necessary error correction enhancement while minimizing the additional computation cost and power consumption associated with the more complex algorithm.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260025152A1Trellis assisted bit flipping decoder
Publication Date: 2026.01.22 SK HYNIX INC
  • US20260025152A1 patent drawing
  • US20260025152A1 patent drawing
  • US20260025152A1 patent drawing

AI summary

Techniques related to improving the error correction performance of a bit-flipping (BF) decoder for decoding a codeword using one or more trellis decoders are described. In some examples, the BF decoder can identify a set of unsatisfied check nodes among a set of check nodes that can be decoded using a trellis decoder. The trellis decoder can perform trellis decoding on the set of unsatisfied check nodes and variable nodes connected to the set of unsatisfied check nodes to determine bit values of the variable nodes to resolve the set of unsatisfied check nodes identified by the BF decoding. The BF decoder can use the bit values of the variable nodes determined by the trellis decoding in a next iteration of the BF decoding to decode the codeword.