Trellis Decoder Rate Matching via Periodic Bit Erasure
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Solution Overview
Problem
The existing decoder for wireless communication systems using trellis diagrams is restricted by the requirement that the number of coded bits per branch must be a common multiple of the number of bits per symbol and the code rate, limiting flexibility in setting transmission speed, especially when the code rate's reciprocal is not a natural number.
Innovation Solution
The system employs a bit erasing unit to generate a second bit sequence with a new code rate by periodically erasing bits from the first bit sequence, allowing the construction of a trellis diagram with a number of coded bits per branch equal to the least common multiple of the original code rate and the reciprocal, enabling flexible transmission speed settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the decoder uses a trellis diagram constructed with the common multiple C of the number of bits per symbol and the reciprocal of the code rate, then decoding can be performed using likelihood per symbol, but the code rate is restricted and transmission speed cannot be set flexibly
Solution Approach 1:
The patent introduces a bit erasing unit that dynamically adjusts the code rate by periodically erasing bits from the coded bit sequence. This allows the system to adapt the transmission speed flexibly while maintaining the trellis diagram structure required for accurate decoding. The erasure pattern can be changed to achieve different effective code rates without changing the fundamental decoder architecture.
Solution Approach 2:
The patent changes the parameter of code rate by introducing bit erasure. By controlling the number and position of erased bits, the system can achieve different effective code rates (e.g., 1/2, 2/3, 3/4) from a base convolutional code, thereby enabling flexible transmission speed settings while maintaining compatibility with the trellis-based Viterbi decoder that requires specific code rate structures.
2Adaptability or versatility
If the reciprocal of the code rate is not a natural number, then flexible transmission speed can be achieved, but the existing decoder cannot be used because the number of coded bits per branch must be a common multiple
Solution Approach 1:
The patent applies preliminary action by erasing bits from the coded bit sequence before modulation and transmission. This pre-processing step modifies the code rate to values where the reciprocal is a natural number, ensuring compatibility with standard Viterbi decoders that require such structures. The bit erasure is performed in advance, allowing the use of conventional decoders without modification.
Solution Approach 2:
The bit erasing unit acts as an intermediary between the convolutional encoder and the Viterbi decoder. It transforms the output of the encoder into a form with a modified code rate that is compatible with the decoder's requirements. This intermediary component enables the system to use flexible code rates while maintaining ease of implementation with standard decoding algorithms.
3Adaptability or versatility
If bits are periodically erased to achieve a new code rate, then transmission speed flexibility is improved, but the system complexity increases due to the bit erasing unit
Solution Approach 1:
The patent segments the coded bit sequence into groups and applies erasure patterns to each group. This segmentation approach allows the bit erasing unit to operate in a structured manner, erasing specific positions within each segment while preserving others. The segmented approach simplifies the control logic of the erasing unit and makes the system more manageable compared to a fully adaptive approach.
Data Source
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AI summary
A wireless communication system (1) includes: a transmitter (100) including: a coding unit that generates a first bit sequence by performing convolutional coding on information bits on the basis of a code rate; a bit erasing unit that generates a second bit sequence by erasing one or more bits from the first bit sequence for every predetermined first number of bits; and a modulation unit that generates a symbol by modulation using the second bit sequence; and a receiver (200) including: a demodulation unit that calculates a plurality of first reliabilities that are reliabilities of a plurality of bit sequences that can be derived from the symbol; a likelihood extension unit that generates a plurality of extended bit sequences that are bit sequences each composed of bits for the first number of bits, and generates a plurality of second reliabilities by assigning a plurality of first reliabilities duplicated, as the reliabilities of the plurality of extended bit sequences; and a decoding unit that creates a trellis diagram using the code rate and the plurality of extended bit sequences, and assigns the plurality of second reliabilities to a plurality of branches of the trellis diagram.