Trellis Decoder Memory Access Using Dual-Port RAM
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Solution Overview
Problem
Conventional trellis decoder circuits inefficiently use circuit resources, particularly memory elements, which is problematic in integrated circuits and programmable logic devices where resource optimization is crucial.
Innovation Solution
A method and circuit for accessing a trellis decoder memory that utilizes a dual port random access memory to simultaneously read and write data, employing a read before write feature and toggling write addressing to reduce the number of memory blocks and addresses required, thereby optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional trellis decoder circuits use separate memory blocks for writing and reading data, then data access functionality is achieved, but circuit resource usage increases
Solution Approach 1:
The patent combines separate write memory blocks and read memory blocks into a single dual-port RAM structure. This single memory block has two independent ports that can simultaneously perform write operations through one port and read operations through the other port, eliminating the need for separate memory blocks and reducing overall circuit resource usage.
Solution Approach 2:
The dual-port RAM serves multiple functions simultaneously: it acts as both a write memory block and a read memory block. The same physical memory structure can be accessed through different ports for different operations, making the memory system universal and multi-functional rather than requiring dedicated separate structures for each function.
2Productivity
If multiple memory blocks are used for trellis decoder operations, then simultaneous read and write operations are enabled, but the number of memory elements increases
Solution Approach 1:
The patent merges multiple memory blocks into a single dual-port RAM structure. This single memory block contains both the functionality of separate write and read memory blocks, allowing simultaneous read and write operations through its two independent ports while using fewer total memory elements than would be required for separate memory blocks.
Solution Approach 2:
The patent transitions from a single-port memory architecture to a dual-port memory architecture, adding the dimension of port independence. This allows simultaneous access to the same memory block through two different ports, enabling concurrent read and write operations without requiring multiple separate memory blocks.
3Productivity
If dual port BRAMs are used for memory access, then simultaneous read and write operations are achieved, but resource requirements double compared to single port memory
Solution Approach 1:
The patent merges the functionality of two separate single-port memory blocks into a single dual-port RAM structure. Instead of requiring two independent memory blocks (one for reading, one for writing), the dual-port RAM provides both read and write capabilities in a single integrated structure, halving the overall resource requirements while maintaining simultaneous operation capability.
Data Source
AI summary
A method of accessing a memory of a trellis decoder. The method comprises the steps of writing a first block of data associated with a trellis function to a first memory block; writing a second block of data associated with the trellis function to a second memory block; simultaneously writing a third block of data to a third memory block and reading the second block of data from the second memory block to generate training data; and simultaneously reading data to be decoded from the first memory block and writing a fourth block of data to the first memory block and generating training data associated with the third block of data. A circuit for accessing a memory of a trellis decoder is also described.