Trench Alignment Structures for Nano-FET Lithography Overlay

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, the integration of electronic components becomes more challenging due to issues with registration and overlay errors during lithography processes, leading to damage or destruction of alignment structures during the singulation process.

Innovation Solution

The formation of alignment structures with trenches in the substrate, using anisotropic etching to create precise patterns, followed by conformal deposition of semiconductor layers, allows for accurate alignment and minimizes damage during singulation, enabling precise lithography and implantation processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but registration and overlay errors during lithography processes increase

Engineering Contradiction:

Improveintegration densityVSAvoidregistration and overlay accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces alignment structures with trenches as intermediary reference features between lithography steps. These trench-based alignment marks serve as mediators that enable precise registration and overlay control during multi-step lithography processes, directly addressing the degradation of alignment accuracy when scaling to smaller feature sizes

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces traditional mechanical or photoresist-based alignment methods with optical measurement systems that detect trench structures. This substitution enables more precise alignment measurement through optical interrogation of the trench features, improving registration accuracy beyond what conventional mechanical alignment systems can achieve

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Ease of manufacture

If traditional alignment structures are used, then lithography processes can proceed, but alignment structures are damaged or destroyed during the singulation process

Engineering Contradiction:

Improvelithography processabilityVSAvoidalignment structure integrity

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent creates alignment structures with localized trenches that have specific geometric properties in certain regions while maintaining structural integrity in others. The trench features are designed with local quality variations that enable optical detection while preserving the overall structure's resistance to damage during singulation processes

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The alignment structures with trenches are formed preliminarily before the singulation process. This preliminary formation of robust trench-based alignment marks ensures that accurate alignment references exist throughout subsequent manufacturing steps and remain intact through singulation, eliminating the need for post-singulation alignment structure creation

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces registration and overlay errors, ensuring the integrity of alignment structures and enhancing the precision of semiconductor device manufacturing, particularly in nano-FETs, by allowing for accurate measurement and alignment of photomasks.

Implementation Method 1

forming a plurality of trenches in the first region of the substrate using anisotropic etching

Methodology Applied

Scientific EffectAnisotropic etching:

Implementation Method 2

followed by conformal deposition of semiconductor layers

Methodology Applied

Scientific EffectConformal deposition: Deposition (physical)

Data Source

PatentUS20250309134A1Methods for forming alignment structures with trenches for semiconductor devices

Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of forming a semiconductor device is provided. The method includes providing a substrate having a first region and a second region; forming a plurality of trenches in the first region of the substrate; forming a multi-layer stack over the substrate and in the trenches; and patterning the multi-layer stack and the substrate to form first nanostructures over first fins in the first region and second nanostructures over second fins in the second region, where the multi-layer stack includes at least one of first semiconductor layers and at least one of second semiconductor layer stacked alternately, and the plurality of trenches are in corresponding ones of the first fins.