Trench Capacitor DRAM Alignment Mark Using K1 Process Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The shrinking dimensions of modern integrated circuits require increasingly stringent overlay alignment accuracy during semiconductor fabrication, which is challenging to achieve with current registration methods, particularly in the fabrication of trench-capacitor DRAM devices, leading to potential defects and reliability issues.
Innovation Solution
A method involving the creation of a semiconductor substrate with a device region and an alignment mark region, where trench lines with widths less than 0.5 microns are etched and used to improve alignment accuracy by employing a K1 process that refreshes the profile of the alignment mark trenches, allowing for precise polysilicon layer etching and wafer alignment using an alignment light beam, followed by exposure and development of the active area pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional registration methods are used, then the fabrication process is simple, but alignment accuracy is insufficient for shrinking dimensions
Solution Approach 1:
The alignment mark region is prepared in advance by etching trenches and depositing polysilicon layers before the actual active area patterning. This preliminary preparation creates a dedicated reference structure that enhances alignment accuracy without interfering with the main fabrication flow.
Solution Approach 2:
The wafer surface is divided into separate device region and alignment mark region. The alignment mark region contains dedicated trench structures and polysilicon layers that serve solely for alignment purposes, while the device region contains the actual circuit structures. This segmentation allows optimized processing for each region.
2Manufacturing precision
If alignment mark trenches are etched with standard width, then etching is easier, but alignment precision is insufficient
Solution Approach 1:
The alignment mark trenches are etched with specific dimensional characteristics (width less than 0.5 microns) that differ from standard trenches. These specialized dimensions provide enhanced alignment precision for the optical alignment system while being confined to a dedicated alignment mark region.
3Manufacturing precision
If polysilicon layer is not etched from alignment mark trenches, then material remains for potential reuse, but alignment mark profile becomes degraded
Solution Approach 1:
The polysilicon material is selectively removed from the alignment mark trenches through etching processes. This extraction creates clean, well-defined trench profiles that serve as precise alignment references. The removed material is discarded as the alignment mark function is purely reference-based.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the alignment accuracy of trench-capacitor DRAM devices, ensuring high precision in the formation of active area regions and shallow trench isolation, thereby improving the reliability and performance of the devices.
Implementation Method 1
performing a wafer alignment process comprising irradiating the alignment mark using an alignment light beam that passes through the second photoresist layer, thereby acquiring wafer alignment information
Implementation Method 2
performing an exposure process employing a photomask defining avtive area pattern thereon, thereby transferring the avtive area pattern to the second photoresist layer
Data Source
AI summary
A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.