Trench Capacitor Contact Doping Layout for Lower ESR
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Solution Overview
Problem
Existing integrated circuit trench capacitors have high equivalent series resistance (ESR) due to complex fabrication processes and limited contact regions, which can affect their performance and efficiency.
Innovation Solution
The method involves etching trenches in a semiconductor layer, forming a trench dielectric layer, and depositing a doped polysilicon layer within the trenches to create a polysilicon bridge. A blanket dopant implant is used to increase the doping level of the polysilicon bridge and form a larger contact region, reducing ESR by increasing the flow rate of dopant precursor gases while maintaining other gas flow rates constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a blanket dopant implant is used to form a larger contact region, then the ESR is reduced, but the doping level control becomes more challenging
Solution Approach 1:
The patent changes the flow rate parameter of the dopant precursor gas during polysilicon deposition to control the doping level. By increasing the dopant gas flow rate while keeping other gas flow rates constant, the doping level in the polysilicon layer is increased, which reduces the ESR of the trench capacitor without requiring additional implantation steps
2Reliability
If the doping level of polysilicon is increased by increasing dopant precursor gas flow rate, then the ESR is reduced, but the process complexity increases
Solution Approach 1:
The patent merges the polysilicon deposition and doping steps into a single process by adding dopant precursor gas during the chemical vapor deposition. This eliminates the need for separate implantation steps and masks, reducing fabrication process complexity while achieving the desired doping level to reduce ESR
3Reliability
If the contact region is enlarged through blanket implant, then the ESR is reduced, but the manufacturing precision of contact region formation is compromised
Solution Approach 1:
The patent performs preliminary doping during the polysilicon layer formation before subsequent processing steps. By incorporating dopant into the polysilicon layer during deposition, the contact region is pre-formed with appropriate doping levels, eliminating the need for later implantation steps that would require precise mask alignment and reducing manufacturing precision issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the ESR of trench capacitors to below 0.6Ω, improving their performance and efficiency while simplifying the fabrication process by eliminating the need for additional masks and reducing variation across wafers.
Implementation Method 1
forming a doped polysilicon layer over the trench dielectric layer and within the trenches
Implementation Method 2
directing a blanket implant of a first dopant to the polysilicon bridge and to the first surface, the blanket implant forming a contact region extending from the first surface into the semiconductor layer
Data Source
AI summary
A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.