Deep Trench Capacitor Contact Structure Without Stepped Surfaces

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Solution Overview

Problem

Deep trench capacitors occupy significant device area without providing substantial capacitance due to the need for stepped surfaces and extensive connections, which limits their compactness and efficiency in semiconductor devices.

Innovation Solution

The implementation of laterally-insulated contact structures within the area between neighboring deep trenches, using tubular insulating spacers and contact via structures to provide electrical isolation and contact to metallic electrode layers, reduces the horizontal extent of the capacitor and minimizes the device area required for connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional deep trench capacitor structures are used with stepped surfaces and extensive connections, then the capacitor can provide substantial capacitance, but the device area occupied by connections and stepped surfaces increases significantly

Engineering Contradiction:
ImprovecapacitanceVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar capacitor design to a three-dimensional deep trench structure. The capacitor is formed by etching deep trenches into the substrate and filling them with alternating layers of dielectric material and conductive electrodes, creating a vertically stacked configuration. This vertical stacking in the depth dimension allows achieving high capacitance values without proportionally increasing the horizontal device footprint, effectively resolving the contradiction between capacitance and device area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where multiple conductive electrode layers are embedded within dielectric layers inside the deep trench. The electrodes are positioned at different vertical levels and connected to external terminals through contact structures that pass through the dielectric layers. This nested arrangement of electrodes within dielectric within trench walls maximizes the capacitance-generating interface area while confining the overall structure to a compact volume, thereby reducing the device area required for connections.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of operation

If stepped surfaces are used to accommodate multiple electrode layers, then electrical contact to different electrode levels is achieved, but the horizontal extent and device area increase

Engineering Contradiction:
Improveelectrical contactVSAvoiddevice area
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

Instead of using stepped surfaces that extend horizontally to access different electrode levels, the patent employs vertical contact vias that penetrate through the dielectric layers in the depth dimension. Contact structures are formed as vertical columns that pass through multiple dielectric layers to reach the conductive electrodes at different levels. This vertical access method eliminates the need for horizontal stepping, thereby maintaining ease of electrical contact while minimizing the horizontal device area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the contact structure into multiple segmented contact vias, each accessing a specific electrode layer at a particular depth. Each contact via is independently formed and connected to its corresponding electrode, allowing for precise electrical contact to multiple levels without requiring a continuous stepped surface. This segmentation enables compact vertical stacking of contact structures, reducing the horizontal footprint while maintaining full electrical connectivity to all electrode layers.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240304700A1Deep trench capacitor including a compact contact region and methods of forming the same
Publication Date: 2024.09.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240304700A1 patent drawing
  • US20240304700A1 patent drawing
  • US20240304700A1 patent drawing

AI summary

A deep trench capacitor includes at least one deep trench and a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers and continuously extending over the top surface of a substrate and into each of the at least one deep trench. A contact-level dielectric layer overlies the substrate and the layer stack. Contact assemblies extend through the contact-level dielectric layer. A subset of the contact assemblies vertically extend through a respective metallic electrode layer. For example, a first contact assembly includes a first tubular insulating spacer that laterally surrounds a first contact via structure and contacts a cylindrical sidewall of a topmost metallic electrode layer.