Trench Capacitor Structure for Higher Density Without Deeper Etching
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Solution Overview
Problem
Conventional capacitive elements of the MOS type face limitations in achieving high capacitive density due to the viability constraints of increasing trench depth in industrial manufacturing, which restricts the enhancement of capacitive density beyond a certain point.
Innovation Solution
The proposed integrated circuit design includes a semiconductor substrate with trenches that are partially filled with dielectric and semiconductor layers, creating both outer and inner capacitive interfaces, thereby doubling the capacitive density without the need for deep trench etching, allowing for a compromise between manufacturing time and capacitive density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the depth of the trenches is increased to increase capacitive density, then the capacitive density is improved, but the manufacturing time and tool operation duration are worsened
Solution Approach 1:
The patent applies nesting by placing a second capacitive structure inside the first trench, with the second electrode nested within the first electrode's trench. This creates multiple capacitive interfaces (outer and inner surfaces) within the same vertical space, effectively doubling the capacitive density without requiring proportionally deeper trenches, thus resolving the contradiction between capacitive density and etching time.
Solution Approach 2:
The patent transitions from a single-interface capacitive structure to a multi-interface structure by utilizing both the outer surface and the inner surface of the trench as capacitive interfaces. This dimensional expansion from one interface to two interfaces per trench allows achieving higher capacitive density without linearly increasing trench depth, thereby reducing the required etching time.
2Quantity of substance
If the depth of the trenches is increased to increase capacitive density, then the capacitive density is improved, but the productivity of the manufacturing line is worsened
Solution Approach 1:
By nesting the second electrode and its associated dielectric layers within the trench structure, the patent creates additional capacitive interfaces without requiring separate, equally deep trenches. This efficient use of vertical space increases capacitive density while maintaining reasonable etching depths, thus preserving production line productivity.
Solution Approach 2:
The invention utilizes the inner surface of the trench as an additional capacitive interface dimension, effectively creating two capacitive interfaces (outer and inner) from a single trench structure. This doubles the capacitive density contribution per trench without requiring double the trench depth, thereby maintaining manufacturing productivity.
3Quantity of substance
If the depth of the trenches is increased to increase capacitive density, then the capacitive density is improved, but the device complexity is worsened
Solution Approach 1:
The patent nests the second electrode structure within the first trench, creating a compact multi-interface capacitive element. This nesting approach achieves higher capacitive density within a confined structural footprint, avoiding the need for excessively deep or complex external trench arrangements.
Data Source
AI summary
A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.