Trench Capacitor Fabrication Using Direct Deposition

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Solution Overview

Problem

Conventional 3D DRAM fabrication methods face challenges in reducing the size of memory cells and transistors due to excessive buried strap diffusion, leading to short circuiting and merging of buried straps between neighboring trench capacitors, which hinders further integration and miniaturization.

Innovation Solution

The method involves forming connecting structures above the trench capacitors using doped and undoped polysilicon layers, with an active layer and gate structures to electrically connect to the trench capacitors, eliminating the need for conventional diffusion regions and allowing for reduced trench spacing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional 3D DRAM fabrication methods are used with thermal diffusion to form buried straps, then the transistor drain region can be formed, but the diffusion area becomes excessive causing buried strap merging and short circuiting between neighboring trenches

Engineering Contradiction:
Improveprevention of short circuitingVSAvoiddistance between neighboring trenches
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent extracts the harmful thermal diffusion process that causes buried strap merging and replaces it with a direct deposition process. By removing the diffusion step, the buried straps are formed without excessive lateral spread, preventing short circuits between neighboring trenches and enabling reduced spacing.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the formation mechanism parameter from thermal diffusion to direct deposition. This parameter change eliminates the uncontrolled diffusion area while maintaining the electrical connection function, allowing trenches to be placed closer together without risk of merging.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the distance between neighboring trenches is reduced to increase integration, then device capacity increases, but buried strap merging occurs causing short circuiting

Engineering Contradiction:
Improvedevice integration capacityVSAvoidprevention of short circuiting
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The harmful thermal diffusion process is extracted and removed from the fabrication sequence. This eliminates the root cause of buried strap merging, allowing trenches to be positioned closer together for higher integration while maintaining electrical isolation and preventing short circuits.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from planar lateral diffusion to vertical direct deposition. By changing the dimension of material deposition from horizontal spread to vertical placement, the buried straps are formed with precise lateral boundaries, enabling reduced trench spacing without merging.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the distance between neighboring trenches, preventing short circuits and enabling increased integration and miniaturization of semiconductor memory devices.

Implementation Method 1

The connecting structure is formed in the contact openings to electrically connect to the trench capacitors

Methodology Applied
Scientific EffectThermal diffusion: Diffusion

Data Source

PatentUS7638391B2Semiconductor memory device and fabrication method thereof
Publication Date: 2009.12.29 NAN YA TECH
  • US7638391B2 patent drawing
  • US7638391B2 patent drawing
  • US7638391B2 patent drawing

AI summary

A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.