Trench-Type Capacitor Reducing ESL and Connection Layers
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Solution Overview
Problem
Existing thin-film capacitors face challenges in increasing capacitance while maintaining a thin form factor and reducing equivalent series inductance (ESL), particularly in reworkable land-side capacitor designs for portable IT products, where the number of connection electrode layers contributes to increased thickness and cost due to defects.
Innovation Solution
A capacitor design featuring three or more dielectric layers and trenches with alternating electrode layers and lead electrodes extending from the capacitance formation portion to the margin portion, allowing for a reduced number of connection electrode layers and enhanced capacitance through a trench-type structure, which decreases ESL by optimizing electrode layer placement and connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of dielectric layers is increased to increase capacitance, then capacitance is improved, but the thickness and device complexity increase
Solution Approach 1:
The capacitor is divided into multiple cells, each containing a stack of dielectric layers and electrode layers. The trench structure segments the capacitance formation portion from the connection portions, allowing independent optimization of each region. This segmentation enables the capacitor to achieve high capacitance through multiple dielectric layers while reducing the complexity of connection electrode layers by confining connections to specific margin portion regions.
Solution Approach 2:
The invention transitions from a planar capacitor structure to a three-dimensional structure by forming trenches that extend vertically through the substrate. This dimensional change allows dielectric and electrode layers to be stacked vertically within the trench, increasing capacitance density without proportionally increasing the horizontal footprint or connection complexity.
2Area of stationary object
If the capacitor size is decreased to reduce solder ball removal area, then area is improved, but capacitance formation space is reduced
Solution Approach 1:
The invention exploits the vertical dimension by forming trenches that extend through the substrate thickness. This allows the capacitance formation portion to utilize the vertical space within the trench, enabling high capacitance to be achieved within a compact horizontal footprint. The trench structure effectively transforms a two-dimensional area constraint into a three-dimensional volume utilization problem.
Solution Approach 2:
Multiple dielectric layers and electrode layers are nested vertically within the trench structure. The capacitance formation portion contains a stacked arrangement of dielectric layers (first, second, third dielectric layers) and electrode layers (first, second, third electrode layers) that are nested one above another, maximizing capacitance density within the limited trench volume.
3Quantity of substance
If trenches are added to increase surface area for capacitance, then capacitance is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming the trench structure first, then sequentially forming dielectric layers and electrode layers within the trench. This segmentation allows each layer to be formed independently using standard thin-film deposition techniques, reducing overall manufacturing complexity compared to attempting to form all structures simultaneously.
Solution Approach 2:
The trench structure serves multiple functions: it defines the capacitance formation portion, provides vertical stacking space for multiple dielectric and electrode layers, and acts as a containment structure that simplifies connection electrode placement. This multi-functionality reduces the need for additional manufacturing steps and structures.
Data Source
AI summary
A capacitor includes a plurality of cells each including a capacitance formation portion in which a plurality of trenches are positioned and a margin portion disposed around the capacitance formation portion. The cell includes three or more dielectric layers disposed in the capacitance formation portion and extending in the trenches, and three or more electrode layers sequentially stacked with dielectric layers interposed therebetween and extending in the trenches. At least first and second electrode layers have opposite polarities and each include a lead electrode extending from the capacitance formation portion to the margin portion. A lead electrode of the first electrode layer is disposed in a first region disposed to one side of a central portion of a cell, and a lead electrode of the second electrode layer is disposed in a second region disposed on another side of a central portion of the cell.