Trench Capacitor in ETSOI Substrate Using Dielectric Spacer
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Solution Overview
Problem
The formation of trench capacitors in extremely thin semiconductor on insulator (ETSOI) substrates faces challenges due to insufficient thickness of the SOI layer and buried dielectric layer for effective etching, leading to contamination and reduced manufacturing yield from exposed high-k dielectrics and metal elements during CMOS processing.
Innovation Solution
The method involves recessing the capacitor within the trench, forming a dielectric spacer on the sidewalls using the buried dielectric and SOI layers to prevent contamination and electrical shorts, and filling the trench with a conductive material for electrical communication with semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If trench etching is performed in conventional SOI substrates, then trench capacitor can be formed, but the SOI layer and buried dielectric layer are insufficient in thickness leading to contamination and reduced manufacturing yield
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and spacer before the actual trench etching process. The mandrel (formed from sacrificial material like silicon nitride or oxide) and spacer (formed from dielectric material) are prepared in advance to define the trench geometry, allowing controlled etching through the thin SOI layer without direct exposure of underlying layers during the etch process itself.
Solution Approach 2:
The patent uses an intermediary approach by introducing a mandrel structure as a mediator between the etching process and the thin SOI/buried dielectric layers. This mandrel acts as a protective intermediary that enables precise trench formation while preventing contamination and electrical shorts that would otherwise occur in extremely thin substrates.
2Length of moving object
If the SOI layer thickness is reduced for advanced technology nodes, then device scaling is achieved, but etching control becomes insufficient and contamination occurs
Solution Approach 1:
The mandrel and spacer structures are formed in advance before trench etching, establishing precise geometric boundaries that guide the etching process. This preliminary structuring enables accurate trench formation even when the SOI layer thickness is reduced to 50nm or below, maintaining manufacturing precision despite device scaling.
Solution Approach 2:
The patent changes the parameter of trench formation methodology from direct etching to a multi-step process involving mandrel formation, spacer deposition, and controlled etching. This parameter change in the fabrication process enables precise trench formation in thinned SOI layers by using the mandrel-spacer structure as a template that defines etch depth and geometry.
3Ease of manufacture
If high-k dielectrics and metal elements are exposed during CMOS processing, then capacitor functionality is achieved, but contamination and electrical shorts increase
Solution Approach 1:
The mandrel structure serves as an intermediary protective element during CMOS processing. It shields the high-k dielectric and metal elements from contamination sources while allowing the capacitor to be formed. The spacer provides additional protection and defines the interface between the capacitor structure and surrounding CMOS devices, preventing electrical shorts.
Solution Approach 2:
The patent applies preliminary anti-action by forming the mandrel and spacer structures before CMOS processing begins. These structures preemptively prevent contamination and electrical shorts by creating physical barriers and defined interfaces, countacting harmful effects before they can occur during subsequent processing steps.
Data Source
AI summary
A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.