Trench Capacitor Layer Stacking for Tunable Capacitance Density
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in achieving precise control over the formation of trench capacitors to meet advanced device density and performance targets, particularly in reducing device dimensions while maintaining capacitance density without increasing the surface area of the semiconductor substrate.
Innovation Solution
The method involves forming trench capacitor structures with alternating dielectric and conductive layers, where the depth, width, and number of layers are selectively varied to adjust capacitance, and contact plugs are strategically placed to connect to different conductive layers, allowing for customizable capacitance levels through precise etching and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trench capacitor structures with alternating dielectric and conductive layers are used, then capacitance density is improved, but device dimensions must be reduced to meet density targets
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional trench capacitor structures. By etching trenches into the substrate and filling them with alternating dielectric and conductive layers, the capacitor volume is utilized more effectively, increasing capacitance density without proportionally increasing surface area.
Solution Approach 2:
The patent implements nested multilayer structures where conductive layers are embedded within dielectric layers, and both are contained within the trench structure. This nested arrangement maximizes the use of available space within the trench, achieving higher capacitance density in a compact volume.
2Quantity of substance
If trench capacitor structures are used to increase capacitance density, then capacitance levels can be increased, but the surface area of the substrate must not increase
Solution Approach 1:
The invention moves from two-dimensional planar capacitors to three-dimensional trench capacitors by utilizing the vertical dimension through substrate trenches. This allows capacitance to be increased by adding more dielectric-conductive layer pairs vertically within the same footprint, thereby increasing capacitance without increasing substrate surface area.
Solution Approach 2:
The capacitor structure is segmented into multiple discrete dielectric and conductive layers within the trench. By increasing the number of layer pairs, the total capacitance is increased while maintaining the same trench footprint, thus achieving higher capacitance density without expanding the substrate area occupied.
3Manufacturing precision
If precise control over trench capacitor formation is achieved, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent employs preliminary patterning steps to define trench locations and dimensions before trench formation. Mask patterns are prepared in advance with precise dimensions, and the etching process is controlled to achieve the desired trench depth and width. This preliminary preparation enables precise control over the final capacitor geometry while managing process complexity through structured sequencing.
Solution Approach 2:
The manufacturing process incorporates feedback control through monitoring and adjustment of deposition and etching parameters. By measuring trench dimensions and layer thicknesses during fabrication and adjusting process parameters accordingly, precise control over capacitor formation is achieved while maintaining manageable process complexity through closed-loop control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with tailored capacitance levels, satisfying design criteria for integrated circuits like DRAMs by allowing for independent adjustment of trench capacitor dimensions and electrical connections, thereby enhancing device performance and density.
Implementation Method 1
depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, depositing a first conductive layer over the first dielectric layer
Data Source
AI summary
A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.