Rotationally Symmetric Trench Capacitor Layout for Low Warpage

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Solution Overview

Problem

Trench capacitors in semiconductor integrated circuits experience warpage and cracking due to unbalanced stress caused by mirror symmetry in two-dimensional trench arrays, which worsens with increasing density.

Innovation Solution

Implementing a rotationally symmetric layout of capacitors and incorporating air gaps within the trench structures to alleviate stress, using a method that includes depositing dielectric and conducting layers with controlled thicknesses and planarization processes to form capacitor structures with reduced warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If mirror symmetry is used in two-dimensional trench arrays, then manufacturing simplicity is maintained, but warpage and cracking occur due to unbalanced stress

Engineering Contradiction:
Improvetrench array fabrication simplicityVSAvoidIC die and wafer structural integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies asymmetry by intentionally designing trench arrays with non-uniform patterns, including varying trench densities, depths, and orientations in different regions. This asymmetric configuration balances stress distribution across the substrate, preventing warpage and cracking while maintaining manufacturing feasibility through standardized fabrication processes.

Inventive Principle:
Principle #4Asymmetry

2Quantity of substance

If trench density is increased to achieve high power density, then capacitor capacity is improved, but stress concentration worsens leading to more warpage and cracking

Engineering Contradiction:
Improvecapacitor capacity and power densityVSAvoidstress concentration in substrate
Core Design Contradiction:
Quantity of substanceVSStress or pressure

Solution Approach 1:

The patent implements local quality by varying trench characteristics across different regions of the array. High-density regions provide greater capacitor capacity where needed, while low-density regions with larger spacing reduce stress concentration. The trench depth, width, and orientation are locally optimized to balance capacity requirements with stress management in each specific area.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The trench array is segmented into multiple zones with different density levels, depths, and orientations. This segmentation allows the structure to achieve high overall capacity while distributing stress across multiple lower-density regions, preventing stress concentration that would lead to warpage and cracking.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If uniform trench depth and orientation are used, then manufacturing precision is simplified, but stress lines become concentrated causing warpage

Engineering Contradiction:
Improvetrench uniformity and consistencyVSAvoidwafer and IC die flatness
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The patent introduces asymmetry in trench orientation and depth across different regions of the array. By varying the angular orientation and depth of trenches in a non-uniform pattern, stress lines are effectively broken and redistributed, preventing the concentration that causes warpage while maintaining manufacturing precision through controlled fabrication parameters.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20250240981A1Low warpage high density trench capacitor
Publication Date: 2025.07.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250240981A1 patent drawing
  • US20250240981A1 patent drawing
  • US20250240981A1 patent drawing

AI summary

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.