Trench Capacitor Structure for Lower ESR Power Semiconductors
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Solution Overview
Problem
The existing semiconductor capacitor configuration with conductive layers extended to the substrate surface leads to an increased equivalent series resistance (ESR) due to the lengthened current path, especially in regions where the conductive layers are thin inside the trench.
Innovation Solution
A semiconductor device is designed with a first and second conductive layer laminated with a dielectric layer inside a trench on a semiconductor substrate, where the first conductive layer is insulated from the substrate, and the second conductive layer electrically connects to the substrate, allowing for a shorter current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conductive layers are extended to the surface of the semiconductor substrate, then the capacitor structural body can be formed inside the trench, but the equivalent series resistance (ESR) increases due to the lengthened current path
Solution Approach 1:
The patent transitions from a two-dimensional surface extension approach to a three-dimensional trench-based structure. By forming conductive layers inside a trench that extends vertically into the substrate, the current path is shortened while maintaining the capacitor structure. The trench depth provides an additional dimension for optimizing the electrical connection without increasing the surface area footprint.
Solution Approach 2:
Instead of extending conductive layers from the surface outward, the patent inverts the approach by forming the capacitor structure within a trench that goes inward from the surface. The conductive layers are positioned inside the trench with connections made through the trench bottom or sidewalls, reversing the conventional extension direction and thereby shortening the current path.
2Quantity of substance
If conductive layers are formed thin inside the trench, then the capacitor density increases, but the equivalent series resistance (ESR) increases due to the lengthened current path
Solution Approach 1:
The patent implements a nested structure where multiple conductive layers are stacked inside the trench, with each layer nested within the same vertical space. This allows thin conductive layers to be positioned optimally within the trench volume, maximizing capacitor density while maintaining short current paths through the trench bottom connection point.
Solution Approach 2:
By utilizing the vertical dimension of the trench, the patent can stack multiple thin conductive layers at different depths. This three-dimensional arrangement increases the effective capacitor area without increasing the surface footprint, and the trench bottom connection ensures short current paths for all layers regardless of their vertical position.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a trench on a first main surface of a conductive semiconductor substrate. The method includes laminating conductive layers, each of which is a first or a second conductive layer, along a surface normal direction of a side surface of the trench, while forming dielectric layers between a conductive layer closest to the side surface of the trench and the side surface of the trench, and between the corresponding conductive layers; and removing the first conductive layer and the dielectric layer, which are formed on a bottom portion of the trench, to electrically connect the second conductive layer to the semiconductor substrate at the bottom portion of the trench. After a portion of the first main surface, the portion being outside of the trench, is covered with an insulating protective film, the first conductive layer and the dielectric layer are removed.