Trench Capacitor Segmentation for Memory Density
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Solution Overview
Problem
Conventional nonvolatile ferroelectric memory devices have a large area requirement due to the size of their three-dimensional trench capacitors, which increases the size of the memory chip.
Innovation Solution
The solution involves forming multiple nonvolatile ferroelectric capacitors in each trench, with 'L'-shaped storage nodes separated by insulating films, reducing the area occupied by each capacitor to half or a quarter of the conventional size by using a method that includes forming cell transistors, contact nodes, insulating films, ferroelectric layers, and plate lines through specific etching and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional three-dimensional trench capacitor structure is used, then the capacitor can store data nonvolatilely, but the area occupied by each capacitor is large
Solution Approach 1:
The patent divides a single trench into multiple segments, with each segment containing a separate capacitor structure. Multiple storage nodes and ferroelectric layers are formed within the same trench region, effectively segmenting the capacitor functions across different vertical and horizontal positions. This segmentation allows multiple capacitors to share a common trench infrastructure, reducing the total area required per capacitor while maintaining nonvolatile data retention capabilities.
Solution Approach 2:
The patent transitions from a conventional planar capacitor layout to a three-dimensional structure where multiple capacitors are stacked vertically within a trench. By utilizing the vertical dimension within the trench depth, the design accommodates multiple storage nodes and ferroelectric layers at different heights, thereby reducing the horizontal footprint area of each capacitor while preserving the nonvolatile storage function.
2Productivity
If multiple capacitors are formed in each trench, then the memory density increases, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary patterning and deposition steps where insulating films and conductive layers are prepared in advance before forming the multiple storage nodes. Contact holes and isolation structures are pre-formed to facilitate subsequent capacitor fabrication. This preliminary preparation simplifies the overall manufacturing process by organizing complex steps into manageable sequences, enabling high-density capacitor formation without proportionally increasing process complexity.
Solution Approach 2:
The patent implements a nested structure where multiple storage nodes and ferroelectric layers are contained within a single trench. The capacitors are nested vertically, with each capacitor comprising a storage node, ferroelectric layer, and electrode structure that fits within the trench boundaries. This nesting approach allows multiple capacitors to occupy the same horizontal footprint, increasing memory density while utilizing a unified manufacturing template that controls complexity.
Data Source
AI summary
A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench.