Trench Capacitor Warpage Reduction via Segmented Polysilicon
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Solution Overview
Problem
Conventional integrated trench capacitors experience high wafer warpage due to the deep trench process and polysilicon fill process, leading to operational issues in subsequent processing steps, as the warpage exceeds acceptable limits for photolithography and etch tools.
Innovation Solution
The use of a doped polysilicon layer with a higher doping level on top of an undoped polysilicon layer, which balances stress distribution by employing a tensile stress layer and a compressive stress layer respectively, along with an additional annealing process to relax warpage and reduce equivalent series resistance (ESR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a deep trench process and polysilicon fill process are used to form integrated trench capacitors, then high capacitance density is achieved, but wafer warpage increases to over 400 μm
Solution Approach 1:
The polysilicon fill is divided into multiple layers with different doping levels. The first polysilicon layer has a lower doping level while the second polysilicon layer has a higher doping level, creating distinct stress characteristics in each layer that can be independently controlled to manage overall wafer stress and reduce warpage.
Solution Approach 2:
The doping level parameter is varied across different polysilicon layers. By changing the doping concentration from the first layer to the second layer, the stress state of each layer is modified, enabling tension-compression balance and warpage reduction while maintaining the high capacitance density provided by the deep trench structure.
2Reliability
If a single highly doped polysilicon layer is used to fill the trench, then low equivalent series resistance (ESR) is achieved, but wafer warpage exceeds acceptable limits for subsequent processing
Solution Approach 1:
The single polysilicon layer is segmented into multiple layers with different doping levels. This segmentation allows the ESR to be optimized by having highly doped regions while using lower doped regions to control stress, thereby maintaining low overall ESR while reducing warpage to within acceptable limits for photolithography and etch tools.
Solution Approach 2:
Different regions of the polysilicon fill are assigned different doping qualities. The first polysilicon layer has a lower doping level suitable for stress control, while the second polysilicon layer has a higher doping level optimized for low ESR. This local differentiation allows simultaneous optimization of both ESR and warpage control.
3Quantity of substance
If deep trenches are formed in highly doped silicon substrate, then high density capacitor design is achieved, but operational issues occur in subsequent processing steps due to excessive warpage
Solution Approach 1:
The polysilicon fill structure is segmented into multiple layers with varying doping levels, where the first layer provides stress management and the second layer ensures low ESR. This segmented approach reduces wafer warpage to acceptable levels, enabling subsequent photolithography and etch processing to be performed without operational issues while maintaining high capacitor density.
Solution Approach 2:
The doping level parameter is changed across different polysilicon layers to balance stress and reduce warpage. This parameter variation enables the wafer to maintain flatness within acceptable limits for subsequent processing steps, ensuring ease of operation in photolithography and etch tools while preserving the high density capacitor design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces wafer warpage from over 400 μm to less than 100 μm, enabling proper processing and maintaining high capacitance density while minimizing ESR, thus addressing the operational limitations of conventional trench capacitors.
Implementation Method 1
balances stress distribution by employing a tensile stress layer and a compressive stress layer respectively
Implementation Method 2
effectively reduces wafer warpage from over 400 μm to less than 100 μm
Implementation Method 3
along with an additional annealing process to relax warpage and reduce equivalent series resistance (ESR)
Data Source
AI summary
A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.