Trench Capacitor STI Process for Logic Compatibility
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Solution Overview
Problem
The existing STI process for manufacturing trench capacitor DRAM devices is complex, leading to poor critical dimension uniformity, large iso/dense CD bias, and incompatibility with logic processes, which complicates the development of trench capacitor structures and reduces effective capacitor area.
Innovation Solution
The method involves forming STI regions in both memory and logic areas before fabricating trench capacitors, using a patterned mask to etch deep trenches with vertical and curved sidewalls, allowing for better control and compatibility with logic processes, and enhancing capacitor area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the conventional STI etching process is used to form isolation trenches through trench openings, then the trench capacitor structure can be formed, but the critical dimension uniformity deteriorates and iso/dense CD bias increases due to the thick hard mask and complex structure
Solution Approach 1:
The patent applies preliminary action by forming the STI isolation trenches in the logic area before forming the trench capacitors in the memory area. This sequence allows the STI etching to be performed on a simpler structure without the interference of thick hard masks and complex capacitor layers, thereby achieving better critical dimension uniformity and reducing iso/dense CD bias.
2Adaptability or versatility
If the STI process is performed after trench capacitor formation, then the trench capacitor structure can be completed, but the process compatibility with logic devices deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the fabrication process into distinct stages: first forming STI isolation trenches in the logic area, then forming trench capacitors in the memory area. This segmentation allows each process to be optimized independently, enabling the STI process to be compatible with logic device requirements while the capacitor formation can be optimized for memory performance.
3Area of stationary object
If the conventional STI method is used, then the isolation trenches can be formed, but the effective capacitor area is reduced due to the complex etching process and structure
Solution Approach 1:
By performing the STI etching process before forming the trench capacitors, the patent enables better etching control precision. The simpler structure at the time of STI formation allows for more precise etching, which in turn enables larger effective capacitor areas to be achieved with better dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves critical dimension uniformity, reduces iso/dense CD bias, and increases the effective capacitor area by 5% to 15% while ensuring compatibility with logic processes, thereby enhancing quality and reducing costs.
Implementation Method 1
using the photo mask 28 as an etching mask, a plasma dry etching is performed to etch the BARC 26, the hard mask 20, the silicon substrate 12, and a portion of the storage node 24 and node dielectric layer 22 through the memory array area trench openings 30
Data Source
AI summary
A structure of a trench capacitor and method for manufacturing the same. The method includes providing a substrate having a defined memory area and logic area, and performing an STI process to form at least one STI region on the memory area of the substrate and at least one STI region on the logic area of the substrate. Then, a patterned mask is formed on the substrate and the STI region to partially expose the STI region and partially expose the substrate surrounding the STI region. Next, the STI region and the substrate not covered by the mask are etched to from a plurality of deep trench.