Trench Capacitor Transmissive Strap Leakage Reduction
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Solution Overview
Problem
Conventional deep trench capacitors in memory devices fail to meet high density and low leakage requirements, particularly below the 70 nm generation, due to issues like gate induced drain leakage (GIDL) and sub-threshold leakage.
Innovation Solution
A memory device fabrication method involving a substrate with a trench capacitor, conductive column, collar dielectric layer, and transmissive strap formed by selective epitaxial growth, which reduces leakage by precise positioning and doping, and uses asymmetric spacers to optimize process integration and cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional deep trench capacitors are used, then memory device capacity can be increased, but gate induced drain leakage and sub-threshold leakage increase
Solution Approach 1:
The patent applies local quality by creating an asymmetric spacer structure where only one spacer adjacent to the trench is formed, while the other spacer is removed. This localized structural modification针对性地 addresses the leakage issue at the capacitor-trench interface without affecting other regions of the memory device, thereby reducing gate induced drain leakage while maintaining high memory capacity
Solution Approach 2:
The invention implements asymmetry by intentionally forming spacers of different thicknesses or complete absence on opposite sides of the gate structure. Specifically, one spacer adjacent to the trench is formed to provide proper electrical isolation and reduce leakage, while the other spacer is removed to optimize cell performance and reduce sub-threshold leakage, creating an asymmetric configuration that simultaneously addresses multiple conflicting requirements
2Object-generated harmful factors
If single side buried straps are used to reduce leakage, then gate induced drain leakage decreases, but fabrication process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the asymmetric spacer structure before completing the trench capacitor fabrication process. The spacers are created during the gate structure formation stage, and their selective removal or differential formation is performed in advance, which simplifies subsequent processing steps and reduces overall fabrication complexity compared to post-processing approaches
Solution Approach 2:
The invention applies the taking out principle by selectively removing one of the two spacers that would normally surround the gate structure. By extracting or removing the spacer on one side while retaining it on the other side adjacent to the trench, the patent simplifies the structure to achieve the single side buried strap configuration, reducing fabrication complexity while maintaining leakage reduction benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively decreases threshold voltage, increases capacitance, reduces silicon loss, and minimizes gate induced drain leakage and sub-threshold leakage, while enabling low resistance and precise strap formation.
Implementation Method 1
A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column
Data Source
AI summary
A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An opening is formed on the substrate between the collar dielectric layer and the gate structure. Next, a portion of the top dielectric layer and the collar dielectric layer is removed to expose a portion of the conductive column. An insulating layer is deposited on the gate structure and the exposed conductive column, filling the opening. The insulating layer is etched to expose a portion of the capacitor-side region of the substrate and the conductive column. A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column.