Trench Capacitor Design for High Density
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Solution Overview
Problem
Conventional polysilicon-insulator-polysilicon (PIP) capacitors occupy a large area due to their planar shape, hindering the reduction of chip size in semiconductor devices.
Innovation Solution
A capacitor design featuring a trench structure with a polysilicon layer and dielectric layers forming vertical bars, increasing the surface area while maintaining a similar height, allowing for higher capacitance within the same unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar PIP capacitor structure is used, then the capacitor can be easily manufactured, but the chip area occupied is large
Solution Approach 1:
The capacitor structure transitions from a planar two-dimensional configuration to a three-dimensional vertical configuration by forming trenches in the substrate and stacking electrode-dielectric layers vertically. This dimensional change allows the capacitor to achieve higher capacitance within a smaller chip footprint area while maintaining manufacturability through standard semiconductor processing techniques.
2Area of stationary object
If the capacitor area is reduced, then the chip size can be reduced, but the capacitance per unit area decreases
Solution Approach 1:
By stacking multiple electrode-dielectric layers vertically in three dimensions, the total capacitance increases proportionally with the number of layers while the footprint area remains constant. This vertical stacking approach achieves higher capacitance per unit area compared to planar configurations.
Solution Approach 2:
Multiple capacitor structures are nested vertically within the trench, with each layer containing an electrode-dielectric-electrode sandwich structure. The nested arrangement of multiple capacitive elements in series or parallel configuration increases the total capacitance within the same vertical space, effectively increasing capacitance density.
Data Source
AI summary
The disclosure concerns a capacitor including a trench; an insulation layer; a first polysilicon layer; a first patterned dielectric layer; a second polysilicon layer patterned into a plurality of vertical bars in the trench; a second dielectric layer along surfaces of the first dielectric layer and the second patterned polysilicon layer; and a third polysilicon layer on the second dielectric layer.