Trench Cell Structure With Floating Region for Stable Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device manufacturing, low doping accuracy can lead to mutual compensation between semiconductor regions, causing loss of gate control performance and increased turn-on voltage drops due to lateral and vertical diffusion of doped regions and misalignment of trench etching windows.
Innovation Solution
A cell structure with a floating region between trench units, which adjusts the diffusion range of doped regions and stabilizes gate control performance by preventing mutual compensation and allowing for adjustable doping concentrations near deep trenches, thereby maintaining low turn-on voltage drops even with offset etching windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doping concentration is adjusted strictly to control device performance, then gate control performance is maintained, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent introduces a buffer region between the deep trench and shallow trench that is pre-configured with specific doping characteristics. This preliminary structural arrangement prevents direct interaction between oppositely doped regions, thereby maintaining gate control performance without requiring strict doping concentration control during manufacturing.
Solution Approach 2:
The buffer region acts as an intermediary structure between the deep trench and shallow trench. It provides a transition zone that mediates the interaction between regions with opposite conductive properties, preventing mutual compensation while simplifying the doping process requirements.
2Ease of manufacture
If doping accuracy is low, then manufacturing cost decreases, but doped regions diffuse laterally and vertically causing mutual compensation and loss of gate control
Solution Approach 1:
The buffer region serves as a protective intermediary that physically separates regions with opposite doping types. This structure prevents lateral and vertical diffusion of dopants from causing mutual compensation, allowing for lower doping accuracy without compromising gate control performance.
Solution Approach 2:
The buffer region provides a pre-established protective barrier that cushions against the harmful effects of dopant diffusion. By having this buffer structure in place before doping occurs, the patent prevents mutual compensation even when doping accuracy is low.
3Adaptability or versatility
If trench etching window shifts during processing, then manufacturing flexibility increases, but doping concentration near deep trench deviates causing mismatch and increased turn-on voltage drop
Solution Approach 1:
The buffer region is pre-configured with doping characteristics that are optimized for interaction with the deep trench. This preliminary arrangement ensures that even when the shallow trench position shifts due to etching window variations, the buffer region maintains appropriate doping concentration to prevent mismatch and control turn-on voltage drop.
Solution Approach 2:
The buffer region allows for parameter adjustments in doping concentration to accommodate variations in trench positioning. By optimizing the doping parameters of the buffer region, the patent compensates for manufacturing tolerances in the etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed cell structure effectively stabilizes gate control performance and maintains low turn-on voltage drops by adjusting the diffusion range of doped regions and preventing hole channels, enhancing the robustness and current density of semiconductor devices.
Implementation Method 1
a doped region under a shallow trench reaches a periphery of a deep trench through diffusion. Besides a lateral diffusion, there is a vertical longitudinal.
Data Source
AI summary
A cell structure and related semiconductor device. The cell structure includes a semiconductor substrate, which includes a plurality of first and second trench units. A carrier barrier region and an electric field shielding region corresponding to the first and second trench units are provided at a bottom of each trench. Conductive materials are provided in the trenches to correspondingly form two gate regions. A source-body region is provided between adjacent first trench units and in contact with a first metal layer on a top portion of the semiconductor substrate. A floating region is provided between the first and second trench units and is isolated from a second metal layer by an insulating dielectric. More than one source region is provided in the surface of the source-body region close to a side edge of at least one of the first trench units and the second trench units.