Trench-Based Vertical Channel Stabilization in Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices with vertical channels often experience pillar pattern collapse or leaning, which deteriorates device characteristics due to the complexity of forming extended channel dimensions and cell efficiency requirements.
Innovation Solution
A method involving the formation of trench patterns over a substrate with gate insulation layers, gate electrodes, and line patterns that couple the electrodes, eliminating the need for pillar patterns to prevent collapse and leaning, thereby stabilizing vertical channels by using the trench sidewalls as channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If pillar patterns are used to form vertical channels, then channel length is extended, but pillar patterns collapse and lean
Solution Approach 1:
The patent extracts and eliminates the pillar pattern structure entirely, replacing it with trench patterns formed directly in the substrate. This removes the source of collapse and leaning while preserving the vertical channel function through the trench sidewalls.
Solution Approach 2:
Instead of building upward structures (pillars) that are prone to collapse, the patent inverts the approach by forming downward trenches in the substrate. The trench sidewalls naturally provide structural support and prevent the instability issues associated with upward pillar structures.
2Length of moving object
If complex patterns are formed to extend channel dimensions, then channel length is increased, but manufacturing complexity increases
Solution Approach 1:
The patent segments the channel formation into simple trench patterns that can be independently formed and controlled. This segmentation allows for easier manufacturing compared to complex pillar patterns, while still achieving the desired vertical channel extension.
3Length of moving object
If pillar patterns are used to extend channel dimensions, then channel length is increased, but cell efficiency decreases
Solution Approach 1:
The patent transitions from horizontal pillar patterns to vertical trench patterns, utilizing the vertical dimension more effectively. This dimensional change improves cell efficiency by allowing better packing and reduced area occupation while maintaining extended channel length through the vertical trench sidewalls.
Data Source
AI summary
A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trench patterns.