Trench Contact Spacer Layout for Scaled FinFET and Nanowire Contacts
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in multi-gate transistors as device dimensions scale below the 10 nanometer node is exacerbated by constraints on lithographic processes, particularly in the trade-off between critical dimension and spacing of semiconductor features.
Innovation Solution
The implementation of trench contact spacer structures and depopulation techniques, including the use of low-k spacers and selective etching processes, to optimize front-end-of-line (FEOL) and back-end-of-line (BEOL) semiconductor processing, addressing issues of contact resistance and variability in critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then capacity increases, but manufacturing precision deteriorates due to lithographic constraints
Solution Approach 1:
The patent transitions from planar 2D transistors to three-dimensional FinFET structures with vertical channels. This dimensional change allows continued scaling and density improvement while the 3D geometry provides better electrostatic control, effectively bypassing the lithographic resolution limits that constrain conventional 2D scaling.
Solution Approach 2:
The patent implements multi-gate structures where gates wrap around the channel from multiple directions (top and sidewalls), creating a nested configuration. This multi-dimensional gating provides superior short channel control compared to conventional single-top-gate structures, enabling continued scaling despite lithographic constraints.
2Length of moving object
If critical dimension is reduced to increase density, then device capacity increases, but spacing between features deteriorates due to lithographic constraints
Solution Approach 1:
By moving to vertical FinFET structures, the patent reduces the lateral footprint (critical dimension in the plane) while maintaining adequate spacing between features. The vertical dimension provides the additional space needed for proper feature separation and electrostatic control.
Solution Approach 2:
The patent applies different geometries to different regions: vertical fins provide compact lateral footprint for high density, while the extended vertical structures and surrounding isolation regions maintain adequate spacing. The multi-gate configuration provides localized electrostatic control where needed.
3Quantity of substance
If multi-gate transistor scaling is pursued to increase density, then capacity increases, but contact resistance and variability worsen
Solution Approach 1:
The patent forms trench contacts and spacer structures before final transistor fabrication steps. This preliminary action establishes precise contact locations and dimensions early in the process, reducing variability that would otherwise arise from subsequent processing steps.
Solution Approach 2:
The spacer structures self-align to the trench contacts through conformal deposition, automatically defining precise spacing and dimensions without requiring additional lithographic steps. This self-aligned approach reduces variability in contact geometry and position.
Data Source
AI summary
Integrated circuit structures having trench contact spacer structures are described. A structure includes a fin or a vertical stack of horizontal nanowires, a gate stack, and an epitaxial source or drain structure. A first conductive layer is on the epitaxial source or drain structure. A second conductive layer is on the first conductive layer. A first dielectric spacer is along a side of the gate stack and laterally adjacent to the epitaxial source or drain structure, the first conductive layer, and the second conductive layer. A second dielectric spacer is along the first dielectric spacer and vertically over the epitaxial source or drain structure, the first conductive layer, and the second conductive layer. A conductive fill material is on the second conductive layer and laterally adjacent to the second dielectric spacer, wherein the conductive fill material has a lateral width less than a lateral width of the second conductive layer.