Trench Cutoff Ring for Power Semiconductor Area Reduction
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Solution Overview
Problem
The existing power semiconductor devices have a wide cutoff ring fabricated by ion implantation at the periphery, which occupies a considerable area of the chip, leading to reduced utilization ratio and increased fabrication costs.
Innovation Solution
A power semiconductor device with a cutoff ring featuring at least one trench and a silicon dioxide dielectric layer covering the trench and active area, where ions are implanted into the trench to form an implant area, allowing for a shorter width of the cutoff ring while maintaining high voltage blocking performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ions are implanted at the periphery of the power semiconductor device to form a cutoff ring, then the high voltage blocking performance and reliability are improved, but the cutoff ring occupies a considerable area of the chip, reducing the utilization ratio and increasing fabrication costs
Solution Approach 1:
The patent transitions from a planar cutoff ring structure to a three-dimensional structure by etching trenches into the substrate and filling them with conductive material. This vertical dimensionality change allows the cutoff ring to achieve the same electrical isolation function with reduced lateral footprint, directly addressing the area occupation problem while maintaining high voltage blocking performance
Solution Approach 2:
The patent changes the geometric parameters of the cutoff ring by forming deep trenches (e.g., 5-20 μm depth) with specific width-to-depth ratios. By controlling the trench dimensions and fill material properties, the electrical characteristics are optimized to maintain blocking performance while minimizing the lateral area occupied by the cutoff structure
2Reliability
If a wide cutoff ring is formed by ion implantation, then the reliability and high voltage blocking performance are improved, but the fabrication cost increases due to reduced chip area utilization
Solution Approach 1:
By moving the cutoff functionality into the vertical dimension through trench formation, the lateral dimensions are reduced, allowing more devices to be fabricated on the same chip area. This increases manufacturing efficiency and reduces per-unit fabrication costs while maintaining the required reliability through the three-dimensional electrical isolation
Solution Approach 2:
The patent uses composite structures combining the semiconductor substrate, dielectric trench fill material, and conductive cutoff ring material. This composite approach allows optimization of each material's properties for its specific function, achieving reliable electrical isolation with a more area-efficient structure that reduces overall fabrication costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the chip area occupied by the cutoff ring, improves the chip area utilization ratio, and lowers fabrication costs while enhancing the reliability of the cutoff ring by protecting it with a silicon dioxide dielectric layer.
Implementation Method 1
an implant area located below the trench, wherein the implant area is formed by implanting ions into the trench
Implementation Method 2
performing thermal oxidation on the power semiconductor device to form a silicon dioxide dielectric layer covering the trench and a surface of the active area
Data Source
AI summary
The invention provides a power semiconductor device and a method of fabricating the same and a cutoff ring. A cutoff ring located at a periphery of an active area of the power semiconductor device is etched forming at least one trench below which an implant area is formed by implanting ions into the trench, and a silicon dioxide dielectric layer covering the trench and a surface of the active area, are formed. Since the ions are implanted into the trench formed by etching the cutoff ring to thereby increase a depth of the implanted ions and a density of the cutoff ring, a width of the cutoff ring can be shortened to thereby address the technical problem of a considerable area of a chip occupied by the cutoff ring and improve a utilization ratio of the area of the chip so as to lower a cost of fabricating the chip.