Semiconductor Trench Dielectric Deposition for Void-Reduced Gap Fill
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and costs.
Innovation Solution
A method for manufacturing semiconductor devices involves forming semiconductor fins, isolation structures, and gate structures, with surface treatments and atomic layer deposition to modify trench profiles, allowing for efficient deposition of dielectric layers and improving device performance by changing trench profiles from bowling-shape to V-shape, facilitating gap-fill capability and reducing void sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional fabrication processes are used for smaller feature sizes, then geometric size decreases and functional density increases, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent applies preliminary action by performing surface treatments (nitrogen termination, hydrogen termination) on trench surfaces before dielectric layer deposition. This pre-preparation of surface chemistry ensures optimal deposition conditions and film quality, addressing the manufacturing difficulty associated with smaller feature sizes through advance process planning and execution.
Solution Approach 2:
The patent employs parameter changes by modifying surface termination states (from oxygen-terminated to nitrogen-terminated or hydrogen-terminated) and controlling deposition parameters in atomic layer deposition. These parameter adjustments enable precise control over dielectric layer formation, overcoming fabrication challenges at reduced feature sizes through systematic optimization of process parameters.
2Manufacturing precision
If conventional dielectric layer deposition is performed in bowling-shape trenches, then deposition can proceed, but void sizes increase and film quality deteriorates
Solution Approach 1:
The patent changes the chemical parameters of trench surfaces by applying nitrogen termination and hydrogen termination treatments. These parameter changes modify surface energy and chemistry, enabling uniform dielectric layer deposition that fills bowling-shape trenches completely, thereby eliminating voids and improving film quality through controlled surface-state modification.
Solution Approach 2:
The patent replaces purely physical deposition mechanisms with chemically-enhanced deposition processes. By introducing surface termination chemistry (nitrogen and hydrogen termination) before deposition, the process transitions from simple physical vapor deposition to a chemically-controlled deposition mechanism, ensuring uniform film formation and void elimination in complex trench geometries.
3Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs降低, but fabrication process reliability decreases
Solution Approach 1:
The patent maintains device reliability at smaller feature sizes by systematically changing and optimizing process parameters including surface termination states, deposition temperature, and precursor flow rates. These parameter optimizations ensure consistent dielectric layer quality and device performance, enabling continued scaling while maintaining fabrication reliability.
Solution Approach 2:
The patent implements feedback control through sequential surface treatments (nitrogen termination followed by hydrogen termination) and monitored deposition processes. Each step provides feedback on surface state and deposition progress, allowing real-time adjustments to maintain film quality and device reliability as feature sizes decrease and process windows narrow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by improving film quality and reducing void sizes in dielectric layers, thereby addressing the challenges of smaller feature sizes and increasing production efficiency.
Implementation Method 1
depositing a dielectric layer in the trench, the dielectric layer being deposited by sequentially supplying a first precursor and a second precursor into the trench
Implementation Method 2
performing a surface treatment to modify surfaces of the top portion and the bottom portion of the trench, the surface treatment including sequentially supplying a first gas and a second gas into the trench
Data Source
AI summary
A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.